1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DP1Parameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import utils._ 12 13trait HasXSParameter { 14 val XLEN = 64 15 val HasMExtension = true 16 val HasCExtension = true 17 val HasDiv = true 18 val HasIcache = true 19 val HasDcache = true 20 val EnableStoreQueue = false 21 val AddrBits = 64 // AddrBits is used in some cases 22 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 23 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 24 val AddrBytes = AddrBits / 8 // unused 25 val DataBits = XLEN 26 val DataBytes = DataBits / 8 27 val HasFPU = true 28 val FetchWidth = 8 29 val PredictWidth = FetchWidth * 2 30 val EnableBPU = true 31 val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3 32 val EnableRAS = false 33 val HistoryLength = 64 34 val BtbSize = 256 35 // val BtbWays = 4 36 val BtbBanks = PredictWidth 37 // val BtbSets = BtbSize / BtbWays 38 val JbtacSize = 1024 39 val JbtacBanks = 8 40 val RasSize = 16 41 val IBufSize = 64 42 val DecodeWidth = 6 43 val RenameWidth = 6 44 val CommitWidth = 6 45 val BrqSize = 16 46 val IssQueSize = 8 47 val BrTagWidth = log2Up(BrqSize) 48 val NRPhyRegs = 128 49 val PhyRegIdxWidth = log2Up(NRPhyRegs) 50 val NRReadPorts = 14 51 val NRWritePorts = 8 52 val RoqSize = 128 53 val InnerRoqIdxWidth = log2Up(RoqSize) 54 val RoqIdxWidth = InnerRoqIdxWidth + 1 55 val IntDqDeqWidth = 4 56 val FpDqDeqWidth = 4 57 val LsDqDeqWidth = 4 58 val dp1Paremeters = DP1Parameters( 59 IntDqSize = 16, 60 FpDqSize = 16, 61 LsDqSize = 16 62 ) 63 val exuParameters = ExuParameters( 64 JmpCnt = 1, 65 AluCnt = 4, 66 MulCnt = 1, 67 MduCnt = 1, 68 FmacCnt = 0, 69 FmiscCnt = 0, 70 FmiscDivSqrtCnt = 0, 71 LduCnt = 0, 72 StuCnt = 1 73 ) 74} 75 76trait HasXSLog { this: Module => 77 implicit val moduleName: String = this.name 78} 79 80abstract class XSModule extends Module 81 with HasXSParameter 82 with HasExceptionNO 83 with HasXSLog 84 85//remove this trait after impl module logic 86trait NeedImpl { this: Module => 87 override protected def IO[T <: Data](iodef: T): T = { 88 val io = chisel3.experimental.IO(iodef) 89 io <> DontCare 90 io 91 } 92} 93 94abstract class XSBundle extends Bundle 95 with HasXSParameter 96 with HasTageParameter 97 98case class XSConfig 99( 100 FPGAPlatform: Boolean = true, 101 EnableDebug: Boolean = true 102) 103 104object AddressSpace extends HasXSParameter { 105 // (start, size) 106 // address out of MMIO will be considered as DRAM 107 def mmio = List( 108 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 109 (0x40000000L, 0x40000000L) // external devices 110 ) 111 112 def isMMIO(addr: UInt): Bool = mmio.map(range => { 113 require(isPow2(range._2)) 114 val bits = log2Up(range._2) 115 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 116 }).reduce(_ || _) 117} 118 119 120class XSCore(implicit p: XSConfig) extends XSModule { 121 val io = IO(new Bundle { 122 val imem = new SimpleBusC 123 val dmem = new SimpleBusC 124 val mmio = new SimpleBusUC 125 val frontend = Flipped(new SimpleBusUC()) 126 }) 127 128 io.imem <> DontCare 129 130 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 131 132 val front = Module(new Frontend) 133 val backend = Module(new Backend) 134 135 front.io.backend <> backend.io.frontend 136 137 backend.io.memMMU.imem <> DontCare 138 139 val dtlb = TLB( 140 in = backend.io.dmem, 141 mem = dmemXbar.io.in(1), 142 flush = false.B, 143 csrMMU = backend.io.memMMU.dmem 144 )(TLBConfig(name = "dtlb", totalEntry = 64)) 145 dmemXbar.io.in(0) <> dtlb.io.out 146 dmemXbar.io.in(2) <> io.frontend 147 148 io.dmem <> Cache( 149 in = dmemXbar.io.out, 150 mmio = Seq(io.mmio), 151 flush = "b00".U, 152 empty = dtlb.io.cacheEmpty, 153 enable = HasDcache 154 )(CacheConfig(name = "dcache")) 155 156 XSDebug("(req valid, ready | resp valid, ready) \n") 157 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 158 io.dmem.mem.req.valid, 159 io.dmem.mem.req.ready, 160 io.dmem.mem.req.bits.addr, 161 io.dmem.mem.resp.valid, 162 io.dmem.mem.resp.ready, 163 io.dmem.coh.req.valid, 164 io.dmem.coh.req.ready, 165 io.dmem.coh.req.bits.addr, 166 io.dmem.coh.resp.valid, 167 io.dmem.coh.resp.ready, 168 dmemXbar.io.out.req.valid, 169 dmemXbar.io.out.req.ready, 170 dmemXbar.io.out.req.bits.addr, 171 dmemXbar.io.out.resp.valid, 172 dmemXbar.io.out.resp.ready, 173 backend.io.dmem.req.valid, 174 backend.io.dmem.req.ready, 175 backend.io.dmem.req.bits.addr, 176 backend.io.dmem.resp.valid, 177 backend.io.dmem.resp.ready 178 ) 179} 180