1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 17import freechips.rocketchip.tile.HasFPUParameters 18import utils._ 19 20object hartIdCore extends (() => Int) { 21 var x = 0 22 23 def apply(): Int = { 24 x = x + 1 25 x - 1 26 } 27} 28 29case class XSCoreParameters 30( 31 XLEN: Int = 64, 32 HasMExtension: Boolean = true, 33 HasCExtension: Boolean = true, 34 HasDiv: Boolean = true, 35 HasICache: Boolean = true, 36 HasDCache: Boolean = true, 37 EnableStoreQueue: Boolean = true, 38 AddrBits: Int = 64, 39 VAddrBits: Int = 39, 40 PAddrBits: Int = 40, 41 HasFPU: Boolean = true, 42 FetchWidth: Int = 8, 43 EnableBPU: Boolean = true, 44 EnableBPD: Boolean = true, 45 EnableRAS: Boolean = true, 46 EnableLB: Boolean = false, 47 EnableLoop: Boolean = true, 48 EnableSC: Boolean = true, 49 EnbaleTlbDebug: Boolean = false, 50 EnableJal: Boolean = false, 51 EnableUBTB: Boolean = true, 52 HistoryLength: Int = 64, 53 BtbSize: Int = 2048, 54 JbtacSize: Int = 1024, 55 JbtacBanks: Int = 8, 56 RasSize: Int = 16, 57 CacheLineSize: Int = 512, 58 UBtbWays: Int = 16, 59 BtbWays: Int = 2, 60 61 EnableL1plusPrefetcher: Boolean = true, 62 IBufSize: Int = 32, 63 DecodeWidth: Int = 6, 64 RenameWidth: Int = 6, 65 CommitWidth: Int = 6, 66 BrqSize: Int = 32, 67 FtqSize: Int = 48, 68 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 69 IssQueSize: Int = 12, 70 NRPhyRegs: Int = 160, 71 NRIntReadPorts: Int = 14, 72 NRIntWritePorts: Int = 8, 73 NRFpReadPorts: Int = 14, 74 NRFpWritePorts: Int = 8, 75 LoadQueueSize: Int = 64, 76 StoreQueueSize: Int = 48, 77 RoqSize: Int = 192, 78 dpParams: DispatchParameters = DispatchParameters( 79 IntDqSize = 16, 80 FpDqSize = 16, 81 LsDqSize = 16, 82 IntDqDeqWidth = 4, 83 FpDqDeqWidth = 4, 84 LsDqDeqWidth = 4 85 ), 86 exuParameters: ExuParameters = ExuParameters( 87 JmpCnt = 1, 88 AluCnt = 4, 89 MulCnt = 0, 90 MduCnt = 2, 91 FmacCnt = 4, 92 FmiscCnt = 2, 93 FmiscDivSqrtCnt = 0, 94 LduCnt = 2, 95 StuCnt = 2 96 ), 97 LoadPipelineWidth: Int = 2, 98 StorePipelineWidth: Int = 2, 99 StoreBufferSize: Int = 16, 100 RefillSize: Int = 512, 101 TlbEntrySize: Int = 32, 102 TlbSPEntrySize: Int = 4, 103 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 104 PtwSPEntrySize: Int = 16, 105 PtwL1EntrySize: Int = 16, 106 PtwL2EntrySize: Int = 2048, //(256 * 8) 107 NumPerfCounters: Int = 16, 108 NrExtIntr: Int = 150, 109 PerfRealTime: Boolean = false, 110 PerfIntervalBits: Int = 15 111) 112 113trait HasXSParameter { 114 115 val coreParams = Parameters.get.coreParameters 116 val env = Parameters.get.envParameters 117 118 val XLEN = 64 119 val minFLen = 32 120 val fLen = 64 121 122 def xLen = 64 123 124 val HasMExtension = coreParams.HasMExtension 125 val HasCExtension = coreParams.HasCExtension 126 val HasDiv = coreParams.HasDiv 127 val HasIcache = coreParams.HasICache 128 val HasDcache = coreParams.HasDCache 129 val EnableStoreQueue = coreParams.EnableStoreQueue 130 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 131 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 132 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 133 val AddrBytes = AddrBits / 8 // unused 134 val DataBits = XLEN 135 val DataBytes = DataBits / 8 136 val HasFPU = coreParams.HasFPU 137 val FetchWidth = coreParams.FetchWidth 138 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 139 val EnableBPU = coreParams.EnableBPU 140 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 141 val EnableRAS = coreParams.EnableRAS 142 val EnableLB = coreParams.EnableLB 143 val EnableLoop = coreParams.EnableLoop 144 val EnableSC = coreParams.EnableSC 145 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 146 val HistoryLength = coreParams.HistoryLength 147 val BtbSize = coreParams.BtbSize 148 // val BtbWays = 4 149 val BtbBanks = PredictWidth 150 // val BtbSets = BtbSize / BtbWays 151 val JbtacSize = coreParams.JbtacSize 152 val JbtacBanks = coreParams.JbtacBanks 153 val RasSize = coreParams.RasSize 154 val CacheLineSize = coreParams.CacheLineSize 155 val CacheLineHalfWord = CacheLineSize / 16 156 val ExtHistoryLength = HistoryLength + 64 157 val UBtbWays = coreParams.UBtbWays 158 val BtbWays = coreParams.BtbWays 159 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 160 val IBufSize = coreParams.IBufSize 161 val DecodeWidth = coreParams.DecodeWidth 162 val RenameWidth = coreParams.RenameWidth 163 val CommitWidth = coreParams.CommitWidth 164 val BrqSize = coreParams.BrqSize 165 val FtqSize = coreParams.FtqSize 166 val IssQueSize = coreParams.IssQueSize 167 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 168 val BrTagWidth = log2Up(BrqSize) 169 val NRPhyRegs = coreParams.NRPhyRegs 170 val PhyRegIdxWidth = log2Up(NRPhyRegs) 171 val RoqSize = coreParams.RoqSize 172 val LoadQueueSize = coreParams.LoadQueueSize 173 val StoreQueueSize = coreParams.StoreQueueSize 174 val dpParams = coreParams.dpParams 175 val exuParameters = coreParams.exuParameters 176 val NRIntReadPorts = coreParams.NRIntReadPorts 177 val NRIntWritePorts = coreParams.NRIntWritePorts 178 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 179 val NRFpReadPorts = coreParams.NRFpReadPorts 180 val NRFpWritePorts = coreParams.NRFpWritePorts 181 val LoadPipelineWidth = coreParams.LoadPipelineWidth 182 val StorePipelineWidth = coreParams.StorePipelineWidth 183 val StoreBufferSize = coreParams.StoreBufferSize 184 val RefillSize = coreParams.RefillSize 185 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 186 val TlbEntrySize = coreParams.TlbEntrySize 187 val TlbSPEntrySize = coreParams.TlbSPEntrySize 188 val PtwL3EntrySize = coreParams.PtwL3EntrySize 189 val PtwSPEntrySize = coreParams.PtwSPEntrySize 190 val PtwL1EntrySize = coreParams.PtwL1EntrySize 191 val PtwL2EntrySize = coreParams.PtwL2EntrySize 192 val NumPerfCounters = coreParams.NumPerfCounters 193 val NrExtIntr = coreParams.NrExtIntr 194 val PerfRealTime = coreParams.PerfRealTime 195 val PerfIntervalBits = coreParams.PerfIntervalBits 196 197 val instBytes = if (HasCExtension) 2 else 4 198 val instOffsetBits = log2Ceil(instBytes) 199 200 val icacheParameters = ICacheParameters( 201 tagECC = Some("parity"), 202 dataECC = Some("parity"), 203 replacer = Some("setplru"), 204 nMissEntries = 2 205 ) 206 207 val l1plusCacheParameters = L1plusCacheParameters( 208 tagECC = Some("secded"), 209 dataECC = Some("secded"), 210 replacer = Some("setplru"), 211 nMissEntries = 8 212 ) 213 214 val dcacheParameters = DCacheParameters( 215 tagECC = Some("secded"), 216 dataECC = Some("secded"), 217 replacer = Some("setplru"), 218 nMissEntries = 16, 219 nProbeEntries = 16, 220 nReleaseEntries = 16, 221 nStoreReplayEntries = 16 222 ) 223 224 val LRSCCycles = 100 225 226 227 // cache hierarchy configurations 228 val l1BusDataWidth = 256 229 230 // L2 configurations 231 val L1BusWidth = 256 232 val L2Size = 512 * 1024 // 512KB 233 val L2BlockSize = 64 234 val L2NWays = 8 235 val L2NSets = L2Size / L2BlockSize / L2NWays 236 237 // L3 configurations 238 val L2BusWidth = 256 239 val L3Size = 4 * 1024 * 1024 // 4MB 240 val L3BlockSize = 64 241 val L3NBanks = 4 242 val L3NWays = 8 243 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 244 245 // on chip network configurations 246 val L3BusWidth = 256 247 248 // icache prefetcher 249 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 250 enable = true, 251 _type = "stream", 252 streamParams = StreamPrefetchParameters( 253 streamCnt = 2, 254 streamSize = 4, 255 ageWidth = 4, 256 blockBytes = l1plusCacheParameters.blockBytes, 257 reallocStreamOnMissInstantly = true, 258 cacheName = "icache" 259 ) 260 ) 261 262 // dcache prefetcher 263 val l2PrefetcherParameters = L2PrefetcherParameters( 264 enable = true, 265 _type = "bop", // "stream" or "bop" 266 streamParams = StreamPrefetchParameters( 267 streamCnt = 4, 268 streamSize = 4, 269 ageWidth = 4, 270 blockBytes = L2BlockSize, 271 reallocStreamOnMissInstantly = true, 272 cacheName = "dcache" 273 ), 274 bopParams = BOPParameters( 275 rrTableEntries = 256, 276 rrTagBits = 12, 277 scoreBits = 5, 278 roundMax = 50, 279 badScore = 1, 280 blockBytes = L2BlockSize, 281 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 282 ), 283 ) 284} 285 286trait HasXSLog { 287 this: RawModule => 288 implicit val moduleName: String = this.name 289} 290 291abstract class XSModule extends MultiIOModule 292 with HasXSParameter 293 with HasExceptionNO 294 with HasXSLog 295 with HasFPUParameters { 296 def io: Record 297} 298 299//remove this trait after impl module logic 300trait NeedImpl { 301 this: RawModule => 302 override protected def IO[T <: Data](iodef: T): T = { 303 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 304 val io = chisel3.experimental.IO(iodef) 305 io <> DontCare 306 io 307 } 308} 309 310abstract class XSBundle extends Bundle 311 with HasXSParameter 312 313case class EnviromentParameters 314( 315 FPGAPlatform: Boolean = true, 316 EnableDebug: Boolean = false, 317 EnablePerfDebug: Boolean = true, 318 DualCore: Boolean = false 319) 320 321// object AddressSpace extends HasXSParameter { 322// // (start, size) 323// // address out of MMIO will be considered as DRAM 324// def mmio = List( 325// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 326// (0x40000000L, 0x40000000L) // external devices 327// ) 328 329// def isMMIO(addr: UInt): Bool = mmio.map(range => { 330// require(isPow2(range._2)) 331// val bits = log2Up(range._2) 332// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 333// }).reduce(_ || _) 334// } 335 336 337class XSCore()(implicit p: config.Parameters) extends LazyModule 338 with HasXSParameter 339 with HasExeBlockHelper { 340 // outer facing nodes 341 val frontend = LazyModule(new Frontend()) 342 val l1pluscache = LazyModule(new L1plusCache()) 343 val ptw = LazyModule(new PTW()) 344 val memBlock = LazyModule(new MemBlock( 345 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 346 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 347 fastWakeUpOut = Seq(), 348 slowWakeUpOut = loadExuConfigs, 349 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 350 )) 351 352 lazy val module = new XSCoreImp(this) 353} 354 355class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 356 with HasXSParameter 357 with HasExeBlockHelper { 358 val io = IO(new Bundle { 359 val hartId = Input(UInt(64.W)) 360 val externalInterrupt = new ExternalInterruptIO 361 val l2_pf_enable = Output(Bool()) 362 }) 363 364 val difftestIO = IO(new DifftestBundle()) 365 difftestIO <> DontCare 366 367 val trapIO = IO(new TrapIO()) 368 trapIO <> DontCare 369 370 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 371 AddressSpace.checkMemmap() 372 AddressSpace.printMemmap() 373 374 // to fast wake up fp, mem rs 375 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 376 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 377 378 val ctrlBlock = Module(new CtrlBlock) 379 val integerBlock = Module(new IntegerBlock( 380 fastWakeUpIn = Seq(), 381 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 382 memFastWakeUpIn = loadExuConfigs, 383 fastWakeUpOut = intBlockFastWakeUp, 384 slowWakeUpOut = intBlockSlowWakeUp 385 )) 386 val floatBlock = Module(new FloatBlock( 387 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 388 memSlowWakeUpIn = loadExuConfigs, 389 fastWakeUpOut = Seq(), 390 slowWakeUpOut = fpExuConfigs 391 )) 392 393 val frontend = outer.frontend.module 394 val memBlock = outer.memBlock.module 395 val l1pluscache = outer.l1pluscache.module 396 val ptw = outer.ptw.module 397 398 frontend.io.backend <> ctrlBlock.io.frontend 399 frontend.io.sfence <> integerBlock.io.fenceio.sfence 400 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 401 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 402 403 frontend.io.icacheMemAcq <> l1pluscache.io.req 404 l1pluscache.io.resp <> frontend.io.icacheMemGrant 405 l1pluscache.io.flush := frontend.io.l1plusFlush 406 frontend.io.fencei := integerBlock.io.fenceio.fencei 407 408 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 409 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 410 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 411 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 412 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 413 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 414 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 415 416 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 417 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 418 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 419 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 420 421 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 422 val fpBlockWakeUpInt = fpExuConfigs 423 .zip(floatBlock.io.wakeUpOut.slow) 424 .filter(_._1.writeIntRf) 425 .map(_._2) 426 427 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 428 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 429 .zip(integerBlock.io.wakeUpOut.slow) 430 .filter(_._1.writeFpRf) 431 .map(_._2) 432 433 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 434 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 435 integerBlock.io.memFastWakeUp <> memBlock.io.ldFastWakeUpInt 436 437 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 438 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 439 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 440 441 val wakeUpMem = Seq( 442 integerBlock.io.wakeUpOut, 443 floatBlock.io.wakeUpOut, 444 ) 445 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 446 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 447 // Note: 'WireInit' is used to block 'ready's from memBlock, 448 // we don't need 'ready's from memBlock 449 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 450 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 451 452 integerBlock.io.csrio.hartId <> io.hartId 453 integerBlock.io.csrio.perf <> DontCare 454 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 455 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 456 integerBlock.io.csrio.fpu.isIllegal := false.B 457 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 458 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 459 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 460 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 461 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 462 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 463 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 464 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 465 466 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 467 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 468 469 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 470 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 471 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 472 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 473 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 474 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 475 476 val itlbRepeater = Module(new PTWRepeater()) 477 val dtlbRepeater = Module(new PTWRepeater()) 478 itlbRepeater.io.tlb <> frontend.io.ptw 479 dtlbRepeater.io.tlb <> memBlock.io.ptw 480 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 481 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 482 ptw.io.tlb(0) <> dtlbRepeater.io.ptw 483 ptw.io.tlb(1) <> itlbRepeater.io.ptw 484 ptw.io.sfence <> integerBlock.io.fenceio.sfence 485 ptw.io.csr <> integerBlock.io.csrio.tlb 486 487 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 488 assert(l2PrefetcherParameters._type == "bop") 489 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 490 491 if (!env.FPGAPlatform) { 492 val id = hartIdCore() 493 difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer 494 difftestIO.fromSQ <> memBlock.difftestIO.fromSQ 495 difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR 496 difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq 497 difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic 498 difftestIO.fromPtw <> ptw.difftestIO 499 trapIO <> ctrlBlock.trapIO 500 501 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 502 ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug) 503 ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug) 504 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 505 difftestIO.fromXSCore.r := debugArchReg 506 } 507 508} 509