1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utility._ 28import utils._ 29import xiangshan.backend._ 30import xiangshan.cache.mmu._ 31import xiangshan.frontend._ 32import xiangshan.mem.L1PrefetchFuzzer 33 34abstract class XSModule(implicit val p: Parameters) extends Module 35 with HasXSParameter 36 with HasFPUParameters 37 38//remove this trait after impl module logic 39trait NeedImpl { 40 this: RawModule => 41 override protected def IO[T <: Data](iodef: T): T = { 42 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 43 val io = chisel3.experimental.IO(iodef) 44 io <> DontCare 45 io 46 } 47} 48 49abstract class XSBundle(implicit val p: Parameters) extends Bundle 50 with HasXSParameter 51 52abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 53 with HasXSParameter 54{ 55 // interrupt sinks 56 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 57 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 58 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 59 // outer facing nodes 60 val frontend = LazyModule(new Frontend()) 61 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 62 val backend = LazyModule(new Backend(backendParams)) 63 64 val memBlock = LazyModule(new MemBlock) 65} 66 67class XSCore()(implicit p: config.Parameters) extends XSCoreBase 68 with HasXSDts 69{ 70 lazy val module = new XSCoreImp(this) 71} 72 73class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 74 with HasXSParameter 75 with HasSoCParameter { 76 val io = IO(new Bundle { 77 val hartId = Input(UInt(64.W)) 78 val reset_vector = Input(UInt(PAddrBits.W)) 79 val cpu_halt = Output(Bool()) 80 val l2_pf_enable = Output(Bool()) 81 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 82 val beu_errors = Output(new XSL1BusErrors()) 83 val l2_hint = Input(Valid(new L2ToL1Hint())) 84 }) 85 86 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 87 88 val frontend = outer.frontend.module 89 val backend = outer.backend.module 90 val memBlock = outer.memBlock.module 91 92 val fenceio = backend.io.fenceio 93 94 frontend.io.hartId := io.hartId 95 frontend.io.backend <> backend.io.frontend 96 frontend.io.sfence <> backend.io.frontendSfence 97 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 98 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 99 frontend.io.fencei <> fenceio.fencei 100 101 backend.io.fromTop.hartId := io.hartId 102 backend.io.fromTop.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 103 backend.io.fromTop.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 104 backend.io.fromTop.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 105 backend.io.fromTop.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 106 backend.io.fromTop.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 107 108 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 109 110 backend.io.mem.stIn.zip(memBlock.io.stIn).foreach { case (sink, source) => 111 sink.valid := source.valid 112 sink.bits := 0.U.asTypeOf(sink.bits) 113 sink.bits.robIdx := source.bits.uop.robIdx 114 sink.bits.ssid := source.bits.uop.ssid 115 sink.bits.storeSetHit := source.bits.uop.storeSetHit 116 // The other signals have not been used 117 } 118 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 119 backend.io.mem.lsqEnqIO <> memBlock.io.enqLsq 120 backend.io.mem.sqDeq := memBlock.io.sqDeq 121 backend.io.mem.lqDeq := memBlock.io.lqDeq 122 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 123 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 124 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 125 backend.io.mem.ldaIqFeedback <> memBlock.io.ldaIqFeedback 126 backend.io.mem.staIqFeedback <> memBlock.io.staIqFeedback 127 backend.io.mem.ldCancel <> memBlock.io.ldCancel 128 backend.io.mem.writeBack.zip(memBlock.io.writeback).foreach { case(back, mem) => 129 back <> mem 130 } 131 132 frontend.io.reset_vector := io.reset_vector 133 134 io.cpu_halt := backend.io.toTop.cpuHalted 135 136 // memblock error exception writeback, 1 cycle after normal writeback 137 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 138 139 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 140 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 141 142 memBlock.io.hartId := io.hartId 143 memBlock.io.issue.zip(backend.io.mem.issueUops).foreach { case(memIssue, backIssue) => 144 memIssue <> backIssue 145 } 146 // By default, instructions do not have exceptions when they enter the function units. 147 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 148 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 149 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 150 backend.io.mem.exceptionVAddr := memBlock.io.lsqio.exceptionAddr.vaddr 151 backend.io.mem.csrDistributedUpdate := memBlock.io.csrUpdate 152 backend.io.mem.debugLS := memBlock.io.debug_ls 153 backend.io.mem.lsTopdownInfo := memBlock.io.lsTopdownInfo 154 backend.io.mem.lqCanAccept := memBlock.io.lsqio.lqCanAccept 155 backend.io.mem.sqCanAccept := memBlock.io.lsqio.sqCanAccept 156 157 backend.io.perf.frontendInfo := frontend.io.frontendInfo 158 backend.io.perf.memInfo := memBlock.io.memInfo 159 backend.io.perf.perfEventsFrontend := frontend.getPerf 160 backend.io.perf.perfEventsLsu := memBlock.getPerf 161 backend.io.perf.perfEventsHc := io.perfEvents 162 163 memBlock.io.sfence <> backend.io.mem.sfence 164 memBlock.io.fenceToSbuffer <> backend.io.mem.toSbuffer 165 166 memBlock.io.redirect <> backend.io.mem.redirect 167 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 168 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 169 memBlock.io.lsqio.rob <> backend.io.mem.robLsqIO 170 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 171 memBlock.io.itlb <> frontend.io.ptw 172 memBlock.io.l2_hint.valid := io.l2_hint.valid 173 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 174 175 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 176 io.l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 177 178 // Modules are reset one by one 179 val resetTree = ResetGenNode( 180 Seq( 181 ModuleNode(memBlock), 182 ResetGenNode(Seq( 183 ModuleNode(backend), 184 ResetGenNode(Seq( 185 ResetGenNode(Seq( 186 ModuleNode(frontend) 187 )) 188 )) 189 )) 190 ) 191 ) 192 193 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 194 195} 196