1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.frontend._ 10import xiangshan.mem._ 11import xiangshan.backend.fu.HasExceptionNO 12import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = true, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = true, 36 EnableLB: Boolean = false, 37 EnableLoop: Boolean = false, 38 HistoryLength: Int = 64, 39 BtbSize: Int = 2048, 40 JbtacSize: Int = 1024, 41 JbtacBanks: Int = 8, 42 RasSize: Int = 16, 43 CacheLineSize: Int = 512, 44 UBtbWays: Int = 16, 45 BtbWays: Int = 2, 46 IBufSize: Int = 64, 47 DecodeWidth: Int = 6, 48 RenameWidth: Int = 6, 49 CommitWidth: Int = 6, 50 BrqSize: Int = 12, 51 IssQueSize: Int = 8, 52 NRPhyRegs: Int = 128, 53 NRIntReadPorts: Int = 14, 54 NRIntWritePorts: Int = 8, 55 NRFpReadPorts: Int = 14, 56 NRFpWritePorts: Int = 8, 57 EnableUnifiedLSQ: Boolean = false, 58 LsroqSize: Int = 16, 59 LoadQueueSize: Int = 12, 60 StoreQueueSize: Int = 10, 61 RoqSize: Int = 32, 62 dpParams: DispatchParameters = DispatchParameters( 63 DqEnqWidth = 4, 64 IntDqSize = 24, 65 FpDqSize = 16, 66 LsDqSize = 16, 67 IntDqDeqWidth = 4, 68 FpDqDeqWidth = 4, 69 LsDqDeqWidth = 4, 70 IntDqReplayWidth = 4, 71 FpDqReplayWidth = 4, 72 LsDqReplayWidth = 4 73 ), 74 exuParameters: ExuParameters = ExuParameters( 75 JmpCnt = 1, 76 AluCnt = 4, 77 MulCnt = 0, 78 MduCnt = 2, 79 FmacCnt = 4, 80 FmiscCnt = 2, 81 FmiscDivSqrtCnt = 0, 82 LduCnt = 2, 83 StuCnt = 2 84 ), 85 LoadPipelineWidth: Int = 2, 86 StorePipelineWidth: Int = 2, 87 StoreBufferSize: Int = 16, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbL2EntrySize: Int = 256, // or 512 91 PtwL1EntrySize: Int = 16, 92 PtwL2EntrySize: Int = 256, 93 NumPerfCounters: Int = 16 94) 95 96trait HasXSParameter { 97 98 val core = Parameters.get.coreParameters 99 val env = Parameters.get.envParameters 100 101 val XLEN = core.XLEN 102 val HasMExtension = core.HasMExtension 103 val HasCExtension = core.HasCExtension 104 val HasDiv = core.HasDiv 105 val HasIcache = core.HasICache 106 val HasDcache = core.HasDCache 107 val EnableStoreQueue = core.EnableStoreQueue 108 val AddrBits = core.AddrBits // AddrBits is used in some cases 109 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 110 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 111 val AddrBytes = AddrBits / 8 // unused 112 val DataBits = XLEN 113 val DataBytes = DataBits / 8 114 val HasFPU = core.HasFPU 115 val FetchWidth = core.FectchWidth 116 val PredictWidth = FetchWidth * 2 117 val EnableBPU = core.EnableBPU 118 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 119 val EnableRAS = core.EnableRAS 120 val EnableLB = core.EnableLB 121 val EnableLoop = core.EnableLoop 122 val HistoryLength = core.HistoryLength 123 val BtbSize = core.BtbSize 124 // val BtbWays = 4 125 val BtbBanks = PredictWidth 126 // val BtbSets = BtbSize / BtbWays 127 val JbtacSize = core.JbtacSize 128 val JbtacBanks = core.JbtacBanks 129 val RasSize = core.RasSize 130 val CacheLineSize = core.CacheLineSize 131 val CacheLineHalfWord = CacheLineSize / 16 132 val ExtHistoryLength = HistoryLength + 64 133 val UBtbWays = core.UBtbWays 134 val BtbWays = core.BtbWays 135 val IBufSize = core.IBufSize 136 val DecodeWidth = core.DecodeWidth 137 val RenameWidth = core.RenameWidth 138 val CommitWidth = core.CommitWidth 139 val BrqSize = core.BrqSize 140 val IssQueSize = core.IssQueSize 141 val BrTagWidth = log2Up(BrqSize) 142 val NRPhyRegs = core.NRPhyRegs 143 val PhyRegIdxWidth = log2Up(NRPhyRegs) 144 val RoqSize = core.RoqSize 145 val EnableUnifiedLSQ = core.EnableUnifiedLSQ 146 val LsroqSize = core.LsroqSize // 64 147 val InnerLsroqIdxWidth = log2Up(LsroqSize) 148 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 149 val LoadQueueSize = core.LoadQueueSize 150 val StoreQueueSize = core.StoreQueueSize 151 val dpParams = core.dpParams 152 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 153 val exuParameters = core.exuParameters 154 val NRIntReadPorts = core.NRIntReadPorts 155 val NRIntWritePorts = core.NRIntWritePorts 156 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 157 val NRFpReadPorts = core.NRFpReadPorts 158 val NRFpWritePorts = core.NRFpWritePorts 159 val LoadPipelineWidth = core.LoadPipelineWidth 160 val StorePipelineWidth = core.StorePipelineWidth 161 val StoreBufferSize = core.StoreBufferSize 162 val RefillSize = core.RefillSize 163 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 164 val TlbEntrySize = core.TlbEntrySize 165 val TlbL2EntrySize = core.TlbL2EntrySize 166 val PtwL1EntrySize = core.PtwL1EntrySize 167 val PtwL2EntrySize = core.PtwL2EntrySize 168 val NumPerfCounters = core.NumPerfCounters 169 170 val icacheParameters = ICacheParameters( 171 nMissEntries = 2 172 ) 173 174 val l1plusCacheParameters = L1plusCacheParameters( 175 tagECC = Some("secded"), 176 dataECC = Some("secded"), 177 nMissEntries = 8 178 ) 179 180 val dcacheParameters = DCacheParameters( 181 tagECC = Some("secded"), 182 dataECC = Some("secded"), 183 nMissEntries = 16, 184 nLoadMissEntries = 8, 185 nStoreMissEntries = 8 186 ) 187 188 val LRSCCycles = 100 189 190 191 // cache hierarchy configurations 192 val l1BusDataWidth = 256 193 194 // L2 configurations 195 val L1BusWidth = 256 196 val L2Size = 512 * 1024 // 512KB 197 val L2BlockSize = 64 198 val L2NWays = 8 199 val L2NSets = L2Size / L2BlockSize / L2NWays 200 201 // L3 configurations 202 val L2BusWidth = 256 203 val L3Size = 4 * 1024 * 1024 // 4MB 204 val L3BlockSize = 64 205 val L3NBanks = 4 206 val L3NWays = 8 207 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 208 209 // on chip network configurations 210 val L3BusWidth = 256 211} 212 213trait HasXSLog { this: RawModule => 214 implicit val moduleName: String = this.name 215} 216 217abstract class XSModule extends MultiIOModule 218 with HasXSParameter 219 with HasExceptionNO 220 with HasXSLog 221{ 222 def io: Record 223} 224 225//remove this trait after impl module logic 226trait NeedImpl { this: RawModule => 227 override protected def IO[T <: Data](iodef: T): T = { 228 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 229 val io = chisel3.experimental.IO(iodef) 230 io <> DontCare 231 io 232 } 233} 234 235abstract class XSBundle extends Bundle 236 with HasXSParameter 237 238case class EnviromentParameters 239( 240 FPGAPlatform: Boolean = true, 241 EnableDebug: Boolean = false 242) 243 244object AddressSpace extends HasXSParameter { 245 // (start, size) 246 // address out of MMIO will be considered as DRAM 247 def mmio = List( 248 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 249 (0x40000000L, 0x40000000L) // external devices 250 ) 251 252 def isMMIO(addr: UInt): Bool = mmio.map(range => { 253 require(isPow2(range._2)) 254 val bits = log2Up(range._2) 255 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 256 }).reduce(_ || _) 257} 258 259 260 261class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 262 263 // inner nodes 264 val dcache = LazyModule(new DCache()) 265 val uncache = LazyModule(new Uncache()) 266 val l1pluscache = LazyModule(new L1plusCache()) 267 val ptw = LazyModule(new PTW()) 268 269 // out facing nodes 270 val mem = TLIdentityNode() 271 val mmio = uncache.clientNode 272 273 // L1 to L2 network 274 // ------------------------------------------------- 275 private val l2_xbar = TLXbar() 276 277 private val l2 = LazyModule(new InclusiveCache( 278 CacheParameters( 279 level = 2, 280 ways = L2NWays, 281 sets = L2NSets, 282 blockBytes = L2BlockSize, 283 beatBytes = L1BusWidth / 8, // beatBytes = l1BusDataWidth / 8 284 cacheName = s"L2" 285 ), 286 InclusiveCacheMicroParameters( 287 writeBytes = 8 288 ) 289 )) 290 291 l2_xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 292 l2_xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode 293 l2_xbar := TLBuffer() := DebugIdentityNode() := ptw.node 294 l2.node := TLBuffer() := DebugIdentityNode() := l2_xbar 295 296 297 // L2 to L3 network 298 // ------------------------------------------------- 299 private val l3_xbar = TLXbar() 300 301 private val l3_banks = (0 until L3NBanks) map (i => 302 LazyModule(new InclusiveCache( 303 CacheParameters( 304 level = 3, 305 ways = L3NWays, 306 sets = L3NSets, 307 blockBytes = L3BlockSize, 308 beatBytes = L2BusWidth / 8, 309 cacheName = s"L3_$i" 310 ), 311 InclusiveCacheMicroParameters( 312 writeBytes = 8 313 ) 314 ))) 315 316 l3_xbar := TLBuffer() := DebugIdentityNode() := l2.node 317 318 def bankFilter(bank: Int) = AddressSet( 319 base = bank * L3BlockSize, 320 mask = ~BigInt((L3NBanks -1) * L3BlockSize)) 321 322 for(i <- 0 until L3NBanks) { 323 val filter = TLFilter(TLFilter.mSelectIntersect(bankFilter(i))) 324 l3_banks(i).node := TLBuffer() := DebugIdentityNode() := filter := l3_xbar 325 } 326 327 328 // L3 to memory network 329 // ------------------------------------------------- 330 private val memory_xbar = TLXbar() 331 332 for(i <- 0 until L3NBanks) { 333 memory_xbar := TLBuffer() := TLCacheCork() := TLBuffer() := DebugIdentityNode() := l3_banks(i).node 334 } 335 336 mem := TLBuffer() := TLWidthWidget(L3BusWidth / 8) := memory_xbar 337 338 lazy val module = new XSCoreImp(this) 339} 340 341class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 342 val io = IO(new Bundle { 343 val externalInterrupt = new ExternalInterruptIO 344 }) 345 346 val front = Module(new Frontend) 347 val backend = Module(new Backend) 348 val mem = Module(new Memend) 349 350 val dcache = outer.dcache.module 351 val uncache = outer.uncache.module 352 val l1pluscache = outer.l1pluscache.module 353 val ptw = outer.ptw.module 354 val icache = Module(new ICache) 355 356 front.io.backend <> backend.io.frontend 357 front.io.icacheResp <> icache.io.resp 358 front.io.icacheToTlb <> icache.io.tlb 359 icache.io.req <> front.io.icacheReq 360 icache.io.flush <> front.io.icacheFlush 361 362 icache.io.mem_acquire <> l1pluscache.io.req 363 l1pluscache.io.resp <> icache.io.mem_grant 364 l1pluscache.io.flush := icache.io.l1plusflush 365 icache.io.fencei := backend.io.fencei 366 367 mem.io.backend <> backend.io.mem 368 io.externalInterrupt <> backend.io.externalInterrupt 369 370 ptw.io.tlb(0) <> mem.io.ptw 371 ptw.io.tlb(1) <> front.io.ptw 372 ptw.io.sfence <> backend.io.sfence 373 ptw.io.csr <> backend.io.tlbCsrIO 374 375 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 376 dcache.io.lsu.lsroq <> mem.io.loadMiss 377 dcache.io.lsu.atomics <> mem.io.atomics 378 dcache.io.lsu.store <> mem.io.sbufferToDcache 379 uncache.io.lsroq <> mem.io.uncache 380 381} 382