1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DP1Parameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend.Frontend 11import xiangshan.mem._ 12import xiangshan.utils._ 13 14trait HasXSParameter { 15 val XLEN = 64 16 val HasMExtension = true 17 val HasCExtension = true 18 val HasDiv = true 19 val HasIcache = true 20 val HasDcache = true 21 val EnableStoreQueue = false 22 val AddrBits = 64 // AddrBits is used in some cases 23 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 24 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 25 val L1CacheLineSize = 512 26 val AddrBytes = AddrBits / 8 // unused 27 val DataBits = XLEN 28 val DataBytes = DataBits / 8 29 val HasFPU = true 30 val FetchWidth = 8 31 val IBufSize = 64 32 val DecodeWidth = 6 33 val RenameWidth = 6 34 val CommitWidth = 6 35 val BrqSize = 16 36 val IssQueSize = 8 37 val BrTagWidth = log2Up(BrqSize) 38 val NRPhyRegs = 128 39 val PhyRegIdxWidth = log2Up(NRPhyRegs) 40 val NRReadPorts = 14 41 val NRWritePorts = 8 42 val RoqSize = 32 43 val MoqSize = 16 // 64 44 val InnerRoqIdxWidth = log2Up(RoqSize) 45 val RoqIdxWidth = InnerRoqIdxWidth + 1 46 val InnerMoqIdxWidth = log2Up(MoqSize) 47 val MoqIdxWidth = InnerMoqIdxWidth + 1 48 val IntDqDeqWidth = 4 49 val FpDqDeqWidth = 4 50 val LsDqDeqWidth = 4 51 val dp1Paremeters = DP1Parameters( 52 IntDqSize = 16, 53 FpDqSize = 16, 54 LsDqSize = 16 55 ) 56 val exuParameters = ExuParameters( 57 JmpCnt = 1, 58 AluCnt = 4, 59 MulCnt = 1, 60 MduCnt = 1, 61 FmacCnt = 0, 62 FmiscCnt = 0, 63 FmiscDivSqrtCnt = 0, 64 LduCnt = 0, 65 StuCnt = 1 66 ) 67} 68 69trait HasXSLog { this: Module => 70 implicit val moduleName: String = this.name 71} 72 73abstract class XSModule extends Module 74 with HasXSParameter 75 with HasExceptionNO 76 with HasXSLog 77 78//remove this trait after impl module logic 79trait NeedImpl { this: Module => 80 override protected def IO[T <: Data](iodef: T): T = { 81 val io = chisel3.experimental.IO(iodef) 82 io <> DontCare 83 io 84 } 85} 86 87abstract class XSBundle extends Bundle 88 with HasXSParameter 89 90case class XSConfig 91( 92 FPGAPlatform: Boolean = true, 93 EnableDebug: Boolean = true 94) 95 96object AddressSpace extends HasXSParameter { 97 // (start, size) 98 // address out of MMIO will be considered as DRAM 99 def mmio = List( 100 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 101 (0x40000000L, 0x40000000L) // external devices 102 ) 103 104 def isMMIO(addr: UInt): Bool = mmio.map(range => { 105 require(isPow2(range._2)) 106 val bits = log2Up(range._2) 107 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 108 }).reduce(_ || _) 109} 110 111 112class XSCore(implicit val p: XSConfig) extends XSModule { 113 val io = IO(new Bundle { 114 val imem = new SimpleBusC 115 val dmem = new SimpleBusC 116 val mmio = new SimpleBusUC 117 val frontend = Flipped(new SimpleBusUC()) 118 }) 119 120 io.imem <> DontCare 121 122 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 123 124 val front = Module(new Frontend) 125 val backend = Module(new Backend) 126 val mem = Module(new MemPipeline) 127 128 mem.io := DontCare // FIXME 129 130 front.io.backend <> backend.io.frontend 131 132 backend.io.memMMU.imem <> DontCare 133 134 val dtlb = TLB( 135 in = backend.io.dmem, 136 mem = dmemXbar.io.in(1), 137 flush = false.B, 138 csrMMU = backend.io.memMMU.dmem 139 )(TLBConfig(name = "dtlb", totalEntry = 64)) 140 dmemXbar.io.in(0) <> dtlb.io.out 141 dmemXbar.io.in(2) <> io.frontend 142 143 io.dmem <> Cache( 144 in = dmemXbar.io.out, 145 mmio = Seq(io.mmio), 146 flush = "b00".U, 147 empty = dtlb.io.cacheEmpty, 148 enable = HasDcache 149 )(CacheConfig(name = "dcache")) 150 151 XSDebug("(req valid, ready | resp valid, ready) \n") 152 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 153 io.dmem.mem.req.valid, 154 io.dmem.mem.req.ready, 155 io.dmem.mem.req.bits.addr, 156 io.dmem.mem.resp.valid, 157 io.dmem.mem.resp.ready, 158 io.dmem.coh.req.valid, 159 io.dmem.coh.req.ready, 160 io.dmem.coh.req.bits.addr, 161 io.dmem.coh.resp.valid, 162 io.dmem.coh.resp.ready, 163 dmemXbar.io.out.req.valid, 164 dmemXbar.io.out.req.ready, 165 dmemXbar.io.out.req.bits.addr, 166 dmemXbar.io.out.resp.valid, 167 dmemXbar.io.out.resp.ready, 168 backend.io.dmem.req.valid, 169 backend.io.dmem.req.ready, 170 backend.io.dmem.req.bits.addr, 171 backend.io.dmem.resp.valid, 172 backend.io.dmem.resp.ready 173 ) 174} 175