1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 16import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 17import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 20import freechips.rocketchip.tile.HasFPUParameters 21import utils._ 22 23case class XSCoreParameters 24( 25 XLEN: Int = 64, 26 HasMExtension: Boolean = true, 27 HasCExtension: Boolean = true, 28 HasDiv: Boolean = true, 29 HasICache: Boolean = true, 30 HasDCache: Boolean = true, 31 EnableStoreQueue: Boolean = true, 32 AddrBits: Int = 64, 33 VAddrBits: Int = 39, 34 PAddrBits: Int = 40, 35 HasFPU: Boolean = true, 36 FectchWidth: Int = 8, 37 EnableBPU: Boolean = true, 38 EnableBPD: Boolean = true, 39 EnableRAS: Boolean = true, 40 EnableLB: Boolean = false, 41 EnableLoop: Boolean = false, 42 EnableSC: Boolean = false, 43 HistoryLength: Int = 64, 44 BtbSize: Int = 2048, 45 JbtacSize: Int = 1024, 46 JbtacBanks: Int = 8, 47 RasSize: Int = 16, 48 CacheLineSize: Int = 512, 49 UBtbWays: Int = 16, 50 BtbWays: Int = 2, 51 IBufSize: Int = 64, 52 DecodeWidth: Int = 6, 53 RenameWidth: Int = 6, 54 CommitWidth: Int = 6, 55 BrqSize: Int = 32, 56 IssQueSize: Int = 12, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 IntDqSize = 24, 67 FpDqSize = 24, 68 LsDqSize = 24, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4 72 ), 73 exuParameters: ExuParameters = ExuParameters( 74 JmpCnt = 1, 75 AluCnt = 4, 76 MulCnt = 0, 77 MduCnt = 2, 78 FmacCnt = 4, 79 FmiscCnt = 2, 80 FmiscDivSqrtCnt = 0, 81 LduCnt = 2, 82 StuCnt = 2 83 ), 84 LoadPipelineWidth: Int = 2, 85 StorePipelineWidth: Int = 2, 86 StoreBufferSize: Int = 16, 87 RefillSize: Int = 512, 88 TlbEntrySize: Int = 32, 89 TlbL2EntrySize: Int = 256, // or 512 90 PtwL1EntrySize: Int = 16, 91 PtwL2EntrySize: Int = 256, 92 NumPerfCounters: Int = 16 93) 94 95trait HasXSParameter { 96 97 val core = Parameters.get.coreParameters 98 val env = Parameters.get.envParameters 99 100 val XLEN = 64 101 val minFLen = 32 102 val fLen = 64 103 def xLen = 64 104 val HasMExtension = core.HasMExtension 105 val HasCExtension = core.HasCExtension 106 val HasDiv = core.HasDiv 107 val HasIcache = core.HasICache 108 val HasDcache = core.HasDCache 109 val EnableStoreQueue = core.EnableStoreQueue 110 val AddrBits = core.AddrBits // AddrBits is used in some cases 111 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 112 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 113 val AddrBytes = AddrBits / 8 // unused 114 val DataBits = XLEN 115 val DataBytes = DataBits / 8 116 val HasFPU = core.HasFPU 117 val FetchWidth = core.FectchWidth 118 val PredictWidth = FetchWidth * 2 119 val EnableBPU = core.EnableBPU 120 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 121 val EnableRAS = core.EnableRAS 122 val EnableLB = core.EnableLB 123 val EnableLoop = core.EnableLoop 124 val EnableSC = core.EnableSC 125 val HistoryLength = core.HistoryLength 126 val BtbSize = core.BtbSize 127 // val BtbWays = 4 128 val BtbBanks = PredictWidth 129 // val BtbSets = BtbSize / BtbWays 130 val JbtacSize = core.JbtacSize 131 val JbtacBanks = core.JbtacBanks 132 val RasSize = core.RasSize 133 val CacheLineSize = core.CacheLineSize 134 val CacheLineHalfWord = CacheLineSize / 16 135 val ExtHistoryLength = HistoryLength + 64 136 val UBtbWays = core.UBtbWays 137 val BtbWays = core.BtbWays 138 val IBufSize = core.IBufSize 139 val DecodeWidth = core.DecodeWidth 140 val RenameWidth = core.RenameWidth 141 val CommitWidth = core.CommitWidth 142 val BrqSize = core.BrqSize 143 val IssQueSize = core.IssQueSize 144 val BrTagWidth = log2Up(BrqSize) 145 val NRPhyRegs = core.NRPhyRegs 146 val PhyRegIdxWidth = log2Up(NRPhyRegs) 147 val RoqSize = core.RoqSize 148 val LoadQueueSize = core.LoadQueueSize 149 val StoreQueueSize = core.StoreQueueSize 150 val dpParams = core.dpParams 151 val exuParameters = core.exuParameters 152 val NRIntReadPorts = core.NRIntReadPorts 153 val NRIntWritePorts = core.NRIntWritePorts 154 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 155 val NRFpReadPorts = core.NRFpReadPorts 156 val NRFpWritePorts = core.NRFpWritePorts 157 val LoadPipelineWidth = core.LoadPipelineWidth 158 val StorePipelineWidth = core.StorePipelineWidth 159 val StoreBufferSize = core.StoreBufferSize 160 val RefillSize = core.RefillSize 161 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 162 val TlbEntrySize = core.TlbEntrySize 163 val TlbL2EntrySize = core.TlbL2EntrySize 164 val PtwL1EntrySize = core.PtwL1EntrySize 165 val PtwL2EntrySize = core.PtwL2EntrySize 166 val NumPerfCounters = core.NumPerfCounters 167 168 val icacheParameters = ICacheParameters( 169 nMissEntries = 2 170 ) 171 172 val l1plusCacheParameters = L1plusCacheParameters( 173 tagECC = Some("secded"), 174 dataECC = Some("secded"), 175 nMissEntries = 8 176 ) 177 178 val dcacheParameters = DCacheParameters( 179 tagECC = Some("secded"), 180 dataECC = Some("secded"), 181 nMissEntries = 16, 182 nLoadMissEntries = 8, 183 nStoreMissEntries = 8 184 ) 185 186 val LRSCCycles = 100 187 188 189 // cache hierarchy configurations 190 val l1BusDataWidth = 256 191 192 // L2 configurations 193 val L1BusWidth = 256 194 val L2Size = 512 * 1024 // 512KB 195 val L2BlockSize = 64 196 val L2NWays = 8 197 val L2NSets = L2Size / L2BlockSize / L2NWays 198 199 // L3 configurations 200 val L2BusWidth = 256 201 val L3Size = 4 * 1024 * 1024 // 4MB 202 val L3BlockSize = 64 203 val L3NBanks = 4 204 val L3NWays = 8 205 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 206 207 // on chip network configurations 208 val L3BusWidth = 256 209} 210 211trait HasXSLog { this: RawModule => 212 implicit val moduleName: String = this.name 213} 214 215abstract class XSModule extends MultiIOModule 216 with HasXSParameter 217 with HasExceptionNO 218 with HasXSLog 219 with HasFPUParameters 220{ 221 def io: Record 222} 223 224//remove this trait after impl module logic 225trait NeedImpl { this: RawModule => 226 override protected def IO[T <: Data](iodef: T): T = { 227 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 228 val io = chisel3.experimental.IO(iodef) 229 io <> DontCare 230 io 231 } 232} 233 234abstract class XSBundle extends Bundle 235 with HasXSParameter 236 237case class EnviromentParameters 238( 239 FPGAPlatform: Boolean = true, 240 EnableDebug: Boolean = false 241) 242 243object AddressSpace extends HasXSParameter { 244 // (start, size) 245 // address out of MMIO will be considered as DRAM 246 def mmio = List( 247 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 248 (0x40000000L, 0x40000000L) // external devices 249 ) 250 251 def isMMIO(addr: UInt): Bool = mmio.map(range => { 252 require(isPow2(range._2)) 253 val bits = log2Up(range._2) 254 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 255 }).reduce(_ || _) 256} 257 258 259 260class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 261 262 // outer facing nodes 263 val dcache = LazyModule(new DCache()) 264 val uncache = LazyModule(new Uncache()) 265 val l1pluscache = LazyModule(new L1plusCache()) 266 val ptw = LazyModule(new PTW()) 267 268 lazy val module = new XSCoreImp(this) 269} 270 271class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 272 with HasXSParameter 273 with HasExeBlockHelper 274{ 275 val io = IO(new Bundle { 276 val externalInterrupt = new ExternalInterruptIO 277 }) 278 279 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 280 281 // to fast wake up fp, mem rs 282 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 283 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 284 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 285 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 286 287 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 288 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 289 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 290 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 291 292 val frontend = Module(new Frontend) 293 val ctrlBlock = Module(new CtrlBlock) 294 val integerBlock = Module(new IntegerBlock( 295 fastWakeUpIn = fpBlockFastWakeUpInt, 296 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 297 fastFpOut = intBlockFastWakeUpFp, 298 slowFpOut = intBlockSlowWakeUpFp, 299 fastIntOut = intBlockFastWakeUpInt, 300 slowIntOut = intBlockSlowWakeUpInt 301 )) 302 val floatBlock = Module(new FloatBlock( 303 fastWakeUpIn = intBlockFastWakeUpFp, 304 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 305 fastFpOut = fpBlockFastWakeUpFp, 306 slowFpOut = fpBlockSlowWakeUpFp, 307 fastIntOut = fpBlockFastWakeUpInt, 308 slowIntOut = fpBlockSlowWakeUpInt 309 )) 310 val memBlock = Module(new MemBlock( 311 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 312 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 313 fastFpOut = Seq(), 314 slowFpOut = loadExuConfigs, 315 fastIntOut = Seq(), 316 slowIntOut = loadExuConfigs 317 )) 318 319 val dcache = outer.dcache.module 320 val uncache = outer.uncache.module 321 val l1pluscache = outer.l1pluscache.module 322 val ptw = outer.ptw.module 323 324 325 frontend.io.backend <> ctrlBlock.io.frontend 326 frontend.io.sfence <> integerBlock.io.fenceio.sfence 327 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 328 329 frontend.io.icacheMemAcq <> l1pluscache.io.req 330 l1pluscache.io.resp <> frontend.io.icacheMemGrant 331 l1pluscache.io.flush := frontend.io.l1plusFlush 332 frontend.io.fencei := integerBlock.io.fenceio.fencei 333 334 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 335 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 336 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 337 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 338 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 339 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 340 341 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 342 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 343 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 344 345 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 346 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 347 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 348 349 350 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 351 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 352 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 353 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 354 355 val wakeUpMem = Seq( 356 integerBlock.io.wakeUpIntOut, 357 integerBlock.io.wakeUpFpOut, 358 floatBlock.io.wakeUpIntOut, 359 floatBlock.io.wakeUpFpOut 360 ) 361 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 362 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 363 val raw = WireInit(f) 364 raw 365 })) 366 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 367 val raw = WireInit(s) 368 raw 369 })) 370 371 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 372 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 373 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 374 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 375 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 376 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 377 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 378 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 379 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 380 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 381 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 382 383 floatBlock.io.frm <> integerBlock.io.csrio.frm 384 385 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 386 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 387 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 388 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 389 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 390 391 ptw.io.tlb(0) <> memBlock.io.ptw 392 ptw.io.tlb(1) <> frontend.io.ptw 393 ptw.io.sfence <> integerBlock.io.fenceio.sfence 394 ptw.io.csr <> integerBlock.io.csrio.tlb 395 396 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 397 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 398 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 399 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 400 uncache.io.lsq <> memBlock.io.dcache.uncache 401 402 if (!env.FPGAPlatform) { 403 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 404 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 405 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 406 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 407 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 408 } 409 410} 411