1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.exu.ExuConfig 9import xiangshan.frontend.Frontend 10 11trait HasXSParameter { 12 val XLEN = 64 13 val HasMExtension = true 14 val HasCExtension = true 15 val HasDiv = true 16 val HasIcache = true 17 val HasDcache = true 18 val EnableStoreQueue = false 19 val AddrBits = 64 // AddrBits is used in some cases 20 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 21 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 22 val AddrBytes = AddrBits / 8 // unused 23 val DataBits = XLEN 24 val DataBytes = DataBits / 8 25 val HasFPU = true 26 val FetchWidth = 8 27 val IBufSize = 64 28 val DecodeWidth = 8 29 val DecBufSize = 8 30 val RenameWidth = 6 31 val CommitWidth = 6 32 val BrqSize = 16 33 val BrTagWidth = log2Up(BrqSize) 34 val NRPhyRegs = 96 35 val PhyRegIdxWidth = log2Up(NRPhyRegs) 36 val NRReadPorts = 14 37 val NRWritePorts = 8 38 val RoqSize = 128 39 val RoqIdxWidth = log2Up(RoqSize) 40 val IntDqDeqWidth = 4 41 val FpDqDeqWidth = 4 42 val LsDqDeqWidth = 4 43 val exuConfig = ExuConfig( 44 AluCnt = 4, 45 BruCnt = 1, 46 MulCnt = 1, 47 MduCnt = 1, 48 FmacCnt = 4, 49 FmiscCnt = 1, 50 FmiscDivSqrtCnt = 1, 51 LduCnt = 1, 52 StuCnt = 1 53 ) 54} 55 56abstract class XSModule extends Module 57 with HasXSParameter 58 with HasExceptionNO 59 60//remove this trait after impl module logic 61trait NeedImpl { this: Module => 62 override protected def IO[T <: Data](iodef: T): T = { 63 val io = chisel3.experimental.IO(iodef) 64 io <> DontCare 65 io 66 } 67} 68 69abstract class XSBundle extends Bundle 70 with HasXSParameter 71 72case class XSConfig 73( 74 FPGAPlatform: Boolean = true, 75 EnableDebug: Boolean = false 76) 77 78class XSCore(implicit val p: XSConfig) extends XSModule { 79 val io = IO(new Bundle { 80 val imem = new SimpleBusC 81 val dmem = new SimpleBusC 82 val mmio = new SimpleBusUC 83 val frontend = Flipped(new SimpleBusUC()) 84 }) 85 86 io.imem <> DontCare 87 88 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 89 90 val front = Module(new Frontend) 91 val backend = Module(new Backend) 92 93 front.io.backend <> backend.io.frontend 94 95 backend.io.memMMU.imem <> DontCare 96 97 val dtlb = TLB( 98 in = backend.io.dmem, 99 mem = dmemXbar.io.in(1), 100 flush = false.B, 101 csrMMU = backend.io.memMMU.dmem 102 )(TLBConfig(name = "dtlb", totalEntry = 64)) 103 dmemXbar.io.in(0) <> dtlb.io.out 104 dmemXbar.io.in(2) <> io.frontend 105 106 io.dmem <> Cache( 107 in = dmemXbar.io.out, 108 mmio = Seq(io.mmio), 109 flush = "b00".U, 110 empty = dtlb.io.cacheEmpty, 111 enable = HasDcache 112 )(CacheConfig(name = "dcache")) 113} 114