1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.tile.HasFPUParameters 25import system.HasSoCParameter 26import utils._ 27import utility._ 28import xiangshan.backend._ 29import xiangshan.cache.mmu._ 30import xiangshan.frontend._ 31import xiangshan.mem.L1PrefetchFuzzer 32 33abstract class XSModule(implicit val p: Parameters) extends Module 34 with HasXSParameter 35 with HasFPUParameters 36 37//remove this trait after impl module logic 38trait NeedImpl { 39 this: RawModule => 40 protected def IO[T <: Data](iodef: T): T = { 41 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 42 val io = chisel3.IO(iodef) 43 io <> DontCare 44 io 45 } 46} 47 48abstract class XSBundle(implicit val p: Parameters) extends Bundle 49 with HasXSParameter 50 51abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 52 with HasXSParameter 53{ 54 override def shouldBeInlined: Boolean = false 55 // outer facing nodes 56 val frontend = LazyModule(new Frontend()) 57 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 58 val backend = LazyModule(new Backend(backendParams)) 59 60 val memBlock = LazyModule(new MemBlock) 61 62 memBlock.frontendBridge.icache_node := frontend.icache.clientNode 63 memBlock.frontendBridge.instr_uncache_node := frontend.instrUncache.clientNode 64} 65 66class XSCore()(implicit p: config.Parameters) extends XSCoreBase 67 with HasXSDts 68{ 69 lazy val module = new XSCoreImp(this) 70} 71 72class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 73 with HasXSParameter 74 with HasSoCParameter { 75 val io = IO(new Bundle { 76 val hartId = Input(UInt(64.W)) 77 val reset_vector = Input(UInt(PAddrBits.W)) 78 val cpu_halt = Output(Bool()) 79 val l2_pf_enable = Output(Bool()) 80 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 81 val beu_errors = Output(new XSL1BusErrors()) 82 val l2_hint = Input(Valid(new L2ToL1Hint())) 83 val l2PfqBusy = Input(Bool()) 84 val debugTopDown = new Bundle { 85 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 86 val l2MissMatch = Input(Bool()) 87 val l3MissMatch = Input(Bool()) 88 } 89 }) 90 91 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 92 93 val frontend = outer.frontend.module 94 val backend = outer.backend.module 95 val memBlock = outer.memBlock.module 96 97 frontend.io.hartId := memBlock.io.inner_hartId 98 frontend.io.reset_vector := memBlock.io.inner_reset_vector 99 frontend.io.backend <> backend.io.frontend 100 frontend.io.sfence <> backend.io.frontendSfence 101 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 102 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 103 frontend.io.fencei <> backend.io.fenceio.fencei 104 105 backend.io.fromTop.hartId := memBlock.io.inner_hartId 106 backend.io.fromTop.externalInterrupt := memBlock.io.externalInterrupt 107 108 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 109 110 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 111 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 112 sink.valid := source.valid 113 sink.bits := 0.U.asTypeOf(sink.bits) 114 sink.bits.robIdx := source.bits.uop.robIdx 115 sink.bits.ssid := source.bits.uop.ssid 116 sink.bits.storeSetHit := source.bits.uop.storeSetHit 117 // The other signals have not been used 118 } 119 backend.io.mem.memoryViolation <> memBlock.io.mem_to_ooo.memoryViolation 120 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 121 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 122 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 123 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 124 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 125 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 126 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 127 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 128 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 129 backend.io.mem.ldaIqFeedback <> memBlock.io.mem_to_ooo.ldaIqFeedback 130 backend.io.mem.staIqFeedback <> memBlock.io.mem_to_ooo.staIqFeedback 131 backend.io.mem.hyuIqFeedback <> memBlock.io.mem_to_ooo.hyuIqFeedback 132 backend.io.mem.ldCancel <> memBlock.io.mem_to_ooo.ldCancel 133 backend.io.mem.wakeup <> memBlock.io.mem_to_ooo.wakeup 134 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 135 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 136 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 137 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 138 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 139 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 140 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 141 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 142 143 // memblock error exception writeback, 1 cycle after normal writeback 144 backend.io.mem.s3_delayed_load_error <> memBlock.io.mem_to_ooo.s3_delayed_load_error 145 146 backend.io.mem.exceptionVAddr := memBlock.io.mem_to_ooo.lsqio.vaddr 147 backend.io.mem.csrDistributedUpdate := memBlock.io.mem_to_ooo.csrUpdate 148 backend.io.mem.debugLS := memBlock.io.debug_ls 149 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 150 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 151 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 152 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 153 // Todo: remove it 154 backend.io.fenceio.disableSfence := DontCare 155 156 backend.io.perf.frontendInfo := frontend.io.frontendInfo 157 backend.io.perf.memInfo := memBlock.io.memInfo 158 backend.io.perf.perfEventsFrontend := frontend.getPerf 159 backend.io.perf.perfEventsLsu := memBlock.getPerf 160 backend.io.perf.perfEventsHc := io.perfEvents 161 backend.io.perf.perfEventsCtrl := DontCare 162 backend.io.perf.retiredInstr := DontCare 163 backend.io.perf.ctrlInfo := DontCare 164 165 // top -> memBlock 166 memBlock.io.hartId := io.hartId 167 memBlock.io.outer_reset_vector := io.reset_vector 168 // frontend -> memBlock 169 memBlock.io.inner_beu_errors_icache <> frontend.io.error.toL1BusErrorUnitInfo() 170 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 171 memBlock.io.inner_cpu_halt := backend.io.toTop.cpuHalted 172 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 173 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 174 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 175 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 176 backend.io.mem.issueHysta.map(_.ready := false.B) // this fake port should not be used 177 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 178 179 // By default, instructions do not have exceptions when they enter the function units. 180 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 181 memBlock.io.ooo_to_mem.loadPc := backend.io.mem.loadPcRead 182 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 183 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 184 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 185 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 186 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 187 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 188 189 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 190 191 memBlock.io.redirect <> backend.io.mem.redirect 192 memBlock.io.ooo_to_mem.csrCtrl <> backend.io.mem.csrCtrl 193 memBlock.io.ooo_to_mem.tlbCsr <> backend.io.mem.tlbCsr 194 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 195 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 196 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 197 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 198 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 199 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 200 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 201 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 202 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 203 204 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 205 memBlock.io.l2_hint.valid := io.l2_hint.valid 206 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 207 memBlock.io.l2PfqBusy := io.l2PfqBusy 208 209 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 210 211 // top-down info 212 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 213 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 214 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 215 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 216 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 217 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 218 memBlock.io.debugRolling := backend.io.debugRolling 219 220 io.cpu_halt := memBlock.io.outer_cpu_halt 221 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 222 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 223 io.beu_errors.l2 <> DontCare 224 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 225 // Modules are reset one by one 226 val resetTree = ResetGenNode( 227 Seq( 228 ModuleNode(memBlock), 229 ResetGenNode(Seq( 230 ModuleNode(backend), 231 ResetGenNode(Seq( 232 ResetGenNode(Seq( 233 ModuleNode(frontend) 234 )) 235 )) 236 )) 237 ) 238 ) 239 240 // ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 241 if (debugOpts.FPGAPlatform) { 242 frontend.reset := memBlock.reset_io_frontend 243 backend.reset := memBlock.reset_io_backend 244 } 245} 246