1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import freechips.rocketchip.tilelink.TLBuffer 27import system.HasSoCParameter 28import utility._ 29import utils._ 30import xiangshan.backend._ 31import xiangshan.cache.mmu._ 32import xiangshan.frontend._ 33import xiangshan.backend._ 34import xiangshan.mem.L1PrefetchFuzzer 35 36import scala.collection.mutable.ListBuffer 37 38abstract class XSModule(implicit val p: Parameters) extends Module 39 with HasXSParameter 40 with HasFPUParameters 41 42//remove this trait after impl module logic 43trait NeedImpl { 44 this: RawModule => 45 override protected def IO[T <: Data](iodef: T): T = { 46 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 47 val io = chisel3.experimental.IO(iodef) 48 io <> DontCare 49 io 50 } 51} 52 53abstract class XSBundle(implicit val p: Parameters) extends Bundle 54 with HasXSParameter 55 56abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 57 with HasXSParameter 58{ 59 // interrupt sinks 60 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 61 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 62 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 63 // outer facing nodes 64 val frontend = LazyModule(new Frontend()) 65 val ptw = LazyModule(new L2TLBWrapper()) 66 val ptw_to_l2_buffer = if (!coreParams.softPTW) LazyModule(new TLBuffer) else null 67 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 68 val backend = LazyModule(new Backend(backendParams)) 69 70 if (!coreParams.softPTW) { 71 ptw_to_l2_buffer.node := ptw.node 72 } 73 74 val memBlock = LazyModule(new MemBlock) 75} 76 77class XSCore()(implicit p: config.Parameters) extends XSCoreBase 78 with HasXSDts 79{ 80 lazy val module = new XSCoreImp(this) 81} 82 83class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 84 with HasXSParameter 85 with HasSoCParameter { 86 val io = IO(new Bundle { 87 val hartId = Input(UInt(64.W)) 88 val reset_vector = Input(UInt(PAddrBits.W)) 89 val cpu_halt = Output(Bool()) 90 val l2_pf_enable = Output(Bool()) 91 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 92 val beu_errors = Output(new XSL1BusErrors()) 93 }) 94 95 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 96 97 val frontend = outer.frontend.module 98 val backend = outer.backend.module 99 val memBlock = outer.memBlock.module 100 val ptw = outer.ptw.module 101 val ptw_to_l2_buffer = if (!coreParams.softPTW) outer.ptw_to_l2_buffer.module else null 102 103 val fenceio = backend.io.fenceio 104 105 frontend.io.hartId := io.hartId 106 frontend.io.backend <> backend.io.frontend 107 frontend.io.sfence <> backend.io.frontendSfence 108 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 109 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 110 frontend.io.fencei <> fenceio.fencei 111 112 backend.io.fromTop.hartId := io.hartId 113 backend.io.fromTop.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 114 backend.io.fromTop.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 115 backend.io.fromTop.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 116 backend.io.fromTop.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 117 backend.io.fromTop.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 118 119 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 120 121 backend.io.mem.stIn.zip(memBlock.io.stIn).foreach { case (sink, source) => 122 sink.valid := source.valid 123 sink.bits := 0.U.asTypeOf(sink.bits) 124 sink.bits.robIdx := source.bits.uop.robIdx 125 sink.bits.ssid := source.bits.uop.ssid 126 sink.bits.storeSetHit := source.bits.uop.storeSetHit 127 // The other signals have not been used 128 } 129 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 130 backend.io.mem.lsqEnqIO <> memBlock.io.enqLsq 131 backend.io.mem.sqDeq := memBlock.io.sqDeq 132 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 133 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 134 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 135 backend.io.mem.writeBack <> memBlock.io.writeback 136 137 frontend.io.reset_vector := io.reset_vector 138 139 io.cpu_halt := backend.io.toTop.cpuHalted 140 141 // memblock error exception writeback, 1 cycle after normal writeback 142 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 143 144 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 145 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 146 147 memBlock.io.hartId := io.hartId 148 memBlock.io.issue <> backend.io.mem.issueUops 149 // By default, instructions do not have exceptions when they enter the function units. 150 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 151 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 152 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 153 backend.io.mem.exceptionVAddr := memBlock.io.lsqio.exceptionAddr.vaddr 154 backend.io.mem.csrDistributedUpdate := memBlock.io.csrUpdate 155 156 backend.io.perf.frontendInfo := frontend.io.frontendInfo 157 backend.io.perf.memInfo := memBlock.io.memInfo 158 backend.io.perf.perfEventsFrontend := frontend.getPerf 159 backend.io.perf.perfEventsLsu := memBlock.getPerf 160 backend.io.perf.perfEventsHc := io.perfEvents 161 162 // XSPerfHistogram("fastIn_count", PopCount(allFastUop1.map(_.valid)), true.B, 0, allFastUop1.length, 1) 163// XSPerfHistogram("wakeup_count", PopCount(rfWriteback.map(_.valid)), true.B, 0, rfWriteback.length, 1) 164 165// ctrlBlock.perfinfo.perfEventsEu0 := intExuBlock.getPerf.dropRight(outer.intExuBlock.scheduler.numRs) 166// ctrlBlock.perfinfo.perfEventsEu1 := vecExuBlock.getPerf.dropRight(outer.vecExuBlock.scheduler.numRs) 167 if (!coreParams.softPTW) { 168 memBlock.io.perfEventsPTW := ptw.getPerf 169 } else { 170 memBlock.io.perfEventsPTW := DontCare 171 } 172// ctrlBlock.perfinfo.perfEventsRs := outer.exuBlocks.flatMap(b => b.module.getPerf.takeRight(b.scheduler.numRs)) 173 174 memBlock.io.sfence <> backend.io.mem.sfence 175 memBlock.io.fenceToSbuffer <> backend.io.mem.toSbuffer 176 177 memBlock.io.redirect <> backend.io.mem.redirect 178 memBlock.io.rsfeedback <> backend.io.mem.rsFeedBack 179 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 180 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 181 memBlock.io.lsqio.rob <> backend.io.mem.robLsqIO 182 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 183 184 val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay,frontend.io.ptw, fenceio.sfence, backend.io.tlb, l2tlbParams.ifilterSize) 185 val itlbRepeater2 = PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, ptw.io.tlb(0), fenceio.sfence, backend.io.tlb) 186 val dtlbRepeater1 = PTWFilter(ldtlbParams.fenceDelay, memBlock.io.ptw, fenceio.sfence, backend.io.tlb, l2tlbParams.dfilterSize) 187 val dtlbRepeater2 = PTWRepeaterNB(passReady = false, ldtlbParams.fenceDelay, dtlbRepeater1.io.ptw, ptw.io.tlb(1), fenceio.sfence, backend.io.tlb) 188 ptw.io.sfence <> fenceio.sfence 189 ptw.io.csr.tlb <> backend.io.tlb 190 ptw.io.csr.distribute_csr <> backend.io.csrCustomCtrl.distribute_csr 191 192 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 193 io.l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 194 195 // Modules are reset one by one 196 val resetTree = ResetGenNode( 197 Seq( 198 ModuleNode(memBlock), ModuleNode(dtlbRepeater1), 199 ResetGenNode(Seq( 200 ModuleNode(itlbRepeater2), 201 ModuleNode(ptw), 202 ModuleNode(dtlbRepeater2), 203 ModuleNode(ptw_to_l2_buffer), 204 )), 205 ResetGenNode(Seq( 206 ModuleNode(backend), 207 ResetGenNode(Seq( 208 ResetGenNode(Seq( 209 ModuleNode(frontend), ModuleNode(itlbRepeater1) 210 )) 211 )) 212 )) 213 ) 214 ) 215 216 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 217 218} 219