1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater, Uncache, MemoryOpConstants, MissReq} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 21import freechips.rocketchip.tile.HasFPUParameters 22import sifive.blocks.inclusivecache.PrefetcherIO 23import utils._ 24 25object hartIdCore extends (() => Int) { 26 var x = 0 27 28 def apply(): Int = { 29 x = x + 1 30 x - 1 31 } 32} 33 34case class XSCoreParameters 35( 36 XLEN: Int = 64, 37 HasMExtension: Boolean = true, 38 HasCExtension: Boolean = true, 39 HasDiv: Boolean = true, 40 HasICache: Boolean = true, 41 HasDCache: Boolean = true, 42 EnableStoreQueue: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 BtbSize: Int = 2048, 59 JbtacSize: Int = 1024, 60 JbtacBanks: Int = 8, 61 RasSize: Int = 16, 62 CacheLineSize: Int = 512, 63 UBtbWays: Int = 16, 64 BtbWays: Int = 2, 65 66 EnableL1plusPrefetcher: Boolean = true, 67 IBufSize: Int = 32, 68 DecodeWidth: Int = 6, 69 RenameWidth: Int = 6, 70 CommitWidth: Int = 6, 71 BrqSize: Int = 32, 72 FtqSize: Int = 48, 73 IssQueSize: Int = 12, 74 NRPhyRegs: Int = 160, 75 NRIntReadPorts: Int = 14, 76 NRIntWritePorts: Int = 8, 77 NRFpReadPorts: Int = 14, 78 NRFpWritePorts: Int = 8, 79 LoadQueueSize: Int = 64, 80 StoreQueueSize: Int = 48, 81 RoqSize: Int = 192, 82 dpParams: DispatchParameters = DispatchParameters( 83 IntDqSize = 16, 84 FpDqSize = 16, 85 LsDqSize = 16, 86 IntDqDeqWidth = 4, 87 FpDqDeqWidth = 4, 88 LsDqDeqWidth = 4 89 ), 90 exuParameters: ExuParameters = ExuParameters( 91 JmpCnt = 1, 92 AluCnt = 4, 93 MulCnt = 0, 94 MduCnt = 2, 95 FmacCnt = 4, 96 FmiscCnt = 2, 97 FmiscDivSqrtCnt = 0, 98 LduCnt = 2, 99 StuCnt = 2 100 ), 101 LoadPipelineWidth: Int = 2, 102 StorePipelineWidth: Int = 2, 103 StoreBufferSize: Int = 16, 104 RefillSize: Int = 512, 105 TlbEntrySize: Int = 32, 106 TlbSPEntrySize: Int = 4, 107 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 108 PtwSPEntrySize: Int = 16, 109 PtwL1EntrySize: Int = 16, 110 PtwL2EntrySize: Int = 2048, //(256 * 8) 111 NumPerfCounters: Int = 16, 112 NrExtIntr: Int = 150, 113 PerfRealTime: Boolean = false, 114 PerfIntervalBits: Int = 15 115) 116 117trait HasXSParameter { 118 119 val core = Parameters.get.coreParameters 120 val env = Parameters.get.envParameters 121 122 val XLEN = 64 123 val minFLen = 32 124 val fLen = 64 125 126 def xLen = 64 127 128 val HasMExtension = core.HasMExtension 129 val HasCExtension = core.HasCExtension 130 val HasDiv = core.HasDiv 131 val HasIcache = core.HasICache 132 val HasDcache = core.HasDCache 133 val EnableStoreQueue = core.EnableStoreQueue 134 val AddrBits = core.AddrBits // AddrBits is used in some cases 135 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 136 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 137 val AddrBytes = AddrBits / 8 // unused 138 val DataBits = XLEN 139 val DataBytes = DataBits / 8 140 val HasFPU = core.HasFPU 141 val FetchWidth = core.FetchWidth 142 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 143 val EnableBPU = core.EnableBPU 144 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 145 val EnableRAS = core.EnableRAS 146 val EnableLB = core.EnableLB 147 val EnableLoop = core.EnableLoop 148 val EnableSC = core.EnableSC 149 val EnbaleTlbDebug = core.EnbaleTlbDebug 150 val HistoryLength = core.HistoryLength 151 val BtbSize = core.BtbSize 152 // val BtbWays = 4 153 val BtbBanks = PredictWidth 154 // val BtbSets = BtbSize / BtbWays 155 val JbtacSize = core.JbtacSize 156 val JbtacBanks = core.JbtacBanks 157 val RasSize = core.RasSize 158 val CacheLineSize = core.CacheLineSize 159 val CacheLineHalfWord = CacheLineSize / 16 160 val ExtHistoryLength = HistoryLength + 64 161 val UBtbWays = core.UBtbWays 162 val BtbWays = core.BtbWays 163 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 164 val IBufSize = core.IBufSize 165 val DecodeWidth = core.DecodeWidth 166 val RenameWidth = core.RenameWidth 167 val CommitWidth = core.CommitWidth 168 val BrqSize = core.BrqSize 169 val FtqSize = core.FtqSize 170 val IssQueSize = core.IssQueSize 171 val BrTagWidth = log2Up(BrqSize) 172 val NRPhyRegs = core.NRPhyRegs 173 val PhyRegIdxWidth = log2Up(NRPhyRegs) 174 val RoqSize = core.RoqSize 175 val LoadQueueSize = core.LoadQueueSize 176 val StoreQueueSize = core.StoreQueueSize 177 val dpParams = core.dpParams 178 val exuParameters = core.exuParameters 179 val NRIntReadPorts = core.NRIntReadPorts 180 val NRIntWritePorts = core.NRIntWritePorts 181 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 182 val NRFpReadPorts = core.NRFpReadPorts 183 val NRFpWritePorts = core.NRFpWritePorts 184 val LoadPipelineWidth = core.LoadPipelineWidth 185 val StorePipelineWidth = core.StorePipelineWidth 186 val StoreBufferSize = core.StoreBufferSize 187 val RefillSize = core.RefillSize 188 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 189 val TlbEntrySize = core.TlbEntrySize 190 val TlbSPEntrySize = core.TlbSPEntrySize 191 val PtwL3EntrySize = core.PtwL3EntrySize 192 val PtwSPEntrySize = core.PtwSPEntrySize 193 val PtwL1EntrySize = core.PtwL1EntrySize 194 val PtwL2EntrySize = core.PtwL2EntrySize 195 val NumPerfCounters = core.NumPerfCounters 196 val NrExtIntr = core.NrExtIntr 197 val PerfRealTime = core.PerfRealTime 198 val PerfIntervalBits = core.PerfIntervalBits 199 200 val instBytes = if (HasCExtension) 2 else 4 201 val instOffsetBits = log2Ceil(instBytes) 202 203 val icacheParameters = ICacheParameters( 204 tagECC = Some("parity"), 205 dataECC = Some("parity"), 206 replacer = Some("setplru"), 207 nMissEntries = 2 208 ) 209 210 val l1plusCacheParameters = L1plusCacheParameters( 211 tagECC = Some("secded"), 212 dataECC = Some("secded"), 213 replacer = Some("setplru"), 214 nMissEntries = 8 215 ) 216 217 val dcacheParameters = DCacheParameters( 218 tagECC = Some("secded"), 219 dataECC = Some("secded"), 220 replacer = Some("setplru"), 221 nMissEntries = 16, 222 nProbeEntries = 16, 223 nReleaseEntries = 16, 224 nStoreReplayEntries = 16 225 ) 226 227 val LRSCCycles = 100 228 229 230 // cache hierarchy configurations 231 val l1BusDataWidth = 256 232 233 // L2 configurations 234 val L1BusWidth = 256 235 val L2Size = 512 * 1024 // 512KB 236 val L2BlockSize = 64 237 val L2NWays = 8 238 val L2NSets = L2Size / L2BlockSize / L2NWays 239 240 // L3 configurations 241 val L2BusWidth = 256 242 val L3Size = 4 * 1024 * 1024 // 4MB 243 val L3BlockSize = 64 244 val L3NBanks = 4 245 val L3NWays = 8 246 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 247 248 // on chip network configurations 249 val L3BusWidth = 256 250 251 // icache prefetcher 252 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 253 enable = true, 254 _type = "stream", 255 streamParams = StreamPrefetchParameters( 256 streamCnt = 2, 257 streamSize = 4, 258 ageWidth = 4, 259 blockBytes = l1plusCacheParameters.blockBytes, 260 reallocStreamOnMissInstantly = true, 261 cacheName = "icache" 262 ) 263 ) 264 265 // dcache prefetcher 266 val l2PrefetcherParameters = L2PrefetcherParameters( 267 enable = true, 268 _type = "bop", // "stream" or "bop" 269 streamParams = StreamPrefetchParameters( 270 streamCnt = 4, 271 streamSize = 4, 272 ageWidth = 4, 273 blockBytes = L2BlockSize, 274 reallocStreamOnMissInstantly = true, 275 cacheName = "dcache" 276 ), 277 bopParams = BOPParameters( 278 rrTableEntries = 256, 279 rrTagBits = 12, 280 scoreBits = 5, 281 roundMax = 50, 282 badScore = 1, 283 blockBytes = L2BlockSize, 284 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 285 ), 286 ) 287} 288 289trait HasXSLog { 290 this: RawModule => 291 implicit val moduleName: String = this.name 292} 293 294abstract class XSModule extends MultiIOModule 295 with HasXSParameter 296 with HasExceptionNO 297 with HasXSLog 298 with HasFPUParameters { 299 def io: Record 300} 301 302//remove this trait after impl module logic 303trait NeedImpl { 304 this: RawModule => 305 override protected def IO[T <: Data](iodef: T): T = { 306 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 307 val io = chisel3.experimental.IO(iodef) 308 io <> DontCare 309 io 310 } 311} 312 313abstract class XSBundle extends Bundle 314 with HasXSParameter 315 316case class EnviromentParameters 317( 318 FPGAPlatform: Boolean = true, 319 EnableDebug: Boolean = false, 320 EnablePerfDebug: Boolean = true, 321 DualCore: Boolean = false 322) 323 324// object AddressSpace extends HasXSParameter { 325// // (start, size) 326// // address out of MMIO will be considered as DRAM 327// def mmio = List( 328// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 329// (0x40000000L, 0x40000000L) // external devices 330// ) 331 332// def isMMIO(addr: UInt): Bool = mmio.map(range => { 333// require(isPow2(range._2)) 334// val bits = log2Up(range._2) 335// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 336// }).reduce(_ || _) 337// } 338 339 340class XSCore()(implicit p: config.Parameters) extends LazyModule 341 with HasXSParameter 342 with HasExeBlockHelper { 343 // outer facing nodes 344 val frontend = LazyModule(new Frontend()) 345 val l1pluscache = LazyModule(new L1plusCache()) 346 val ptw = LazyModule(new PTW()) 347 val memBlock = LazyModule(new MemBlock( 348 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 349 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 350 fastWakeUpOut = Seq(), 351 slowWakeUpOut = loadExuConfigs, 352 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 353 )) 354 355 lazy val module = new XSCoreImp(this) 356} 357 358class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 359 with HasXSParameter 360 with HasExeBlockHelper { 361 val io = IO(new Bundle { 362 val hartId = Input(UInt(64.W)) 363 val externalInterrupt = new ExternalInterruptIO 364 val l2_pf_enable = Output(Bool()) 365 }) 366 367 val difftestIO = IO(new DifftestBundle()) 368 difftestIO <> DontCare 369 370 val trapIO = IO(new TrapIO()) 371 trapIO <> DontCare 372 373 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 374 AddressSpace.checkMemmap() 375 AddressSpace.printMemmap() 376 377 // to fast wake up fp, mem rs 378 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 379 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 380 381 val ctrlBlock = Module(new CtrlBlock) 382 val integerBlock = Module(new IntegerBlock( 383 fastWakeUpIn = Seq(), 384 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 385 fastWakeUpOut = intBlockFastWakeUp, 386 slowWakeUpOut = intBlockSlowWakeUp 387 )) 388 val floatBlock = Module(new FloatBlock( 389 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 390 memSlowWakeUpIn = loadExuConfigs, 391 fastWakeUpOut = Seq(), 392 slowWakeUpOut = fpExuConfigs 393 )) 394 395 val frontend = outer.frontend.module 396 val memBlock = outer.memBlock.module 397 val l1pluscache = outer.l1pluscache.module 398 val ptw = outer.ptw.module 399 400 frontend.io.backend <> ctrlBlock.io.frontend 401 frontend.io.sfence <> integerBlock.io.fenceio.sfence 402 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 403 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 404 405 frontend.io.icacheMemAcq <> l1pluscache.io.req 406 l1pluscache.io.resp <> frontend.io.icacheMemGrant 407 l1pluscache.io.flush := frontend.io.l1plusFlush 408 frontend.io.fencei := integerBlock.io.fenceio.fencei 409 410 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 411 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 412 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 413 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 414 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 415 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 416 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 417 418 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 419 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 420 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 421 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 422 423 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 424 val fpBlockWakeUpInt = fpExuConfigs 425 .zip(floatBlock.io.wakeUpOut.slow) 426 .filter(_._1.writeIntRf) 427 .map(_._2) 428 429 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 430 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 431 .zip(integerBlock.io.wakeUpOut.slow) 432 .filter(_._1.writeFpRf) 433 .map(_._2) 434 435 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 436 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 437 438 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 439 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 440 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 441 442 val wakeUpMem = Seq( 443 integerBlock.io.wakeUpOut, 444 floatBlock.io.wakeUpOut, 445 ) 446 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 447 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 448 // Note: 'WireInit' is used to block 'ready's from memBlock, 449 // we don't need 'ready's from memBlock 450 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 451 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 452 453 integerBlock.io.csrio.hartId <> io.hartId 454 integerBlock.io.csrio.perf <> DontCare 455 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 456 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 457 integerBlock.io.csrio.fpu.isIllegal := false.B 458 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 459 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 460 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 461 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 462 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 463 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 464 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 465 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 466 467 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 468 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 469 470 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 471 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 472 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 473 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 474 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 475 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 476 477 val itlbRepeater = Module(new PTWRepeater()) 478 val dtlbRepeater = Module(new PTWRepeater()) 479 itlbRepeater.io.tlb <> frontend.io.ptw 480 dtlbRepeater.io.tlb <> memBlock.io.ptw 481 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 482 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 483 ptw.io.tlb(0) <> dtlbRepeater.io.ptw 484 ptw.io.tlb(1) <> itlbRepeater.io.ptw 485 ptw.io.sfence <> integerBlock.io.fenceio.sfence 486 ptw.io.csr <> integerBlock.io.csrio.tlb 487 488 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 489 assert(l2PrefetcherParameters._type == "bop") 490 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 491 492 if (!env.FPGAPlatform) { 493 val id = hartIdCore() 494 difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer 495 difftestIO.fromSQ <> memBlock.difftestIO.fromSQ 496 difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR 497 difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq 498 difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic 499 difftestIO.fromPtw <> ptw.difftestIO 500 trapIO <> ctrlBlock.trapIO 501 502 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 503 ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug) 504 ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug) 505 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 506 difftestIO.fromXSCore.r := debugArchReg 507 } 508 509} 510