1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DP1Parameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import utils._ 13 14case class XSCoreParameters 15( 16 XLEN: Int = 64, 17 HasMExtension: Boolean = true, 18 HasCExtension: Boolean = true, 19 HasDiv: Boolean = true, 20 HasICache: Boolean = true, 21 HasDCache: Boolean = true, 22 EnableStoreQueue: Boolean = true, 23 AddrBits: Int = 64, 24 VAddrBits: Int = 39, 25 PAddrBits: Int = 32, 26 HasFPU: Boolean = true, 27 FectchWidth: Int = 8, 28 EnableBPU: Boolean = true, 29 EnableBPD: Boolean = false, 30 EnableRAS: Boolean = false, 31 EnableLB: Boolean = false, 32 HistoryLength: Int = 64, 33 BtbSize: Int = 256, 34 JbtacSize: Int = 1024, 35 JbtacBanks: Int = 8, 36 RasSize: Int = 16, 37 IBufSize: Int = 64, 38 DecodeWidth: Int = 6, 39 RenameWidth: Int = 6, 40 CommitWidth: Int = 6, 41 BrqSize: Int = 16, 42 IssQueSize: Int = 8, 43 NRPhyRegs: Int = 128, 44 NRReadPorts: Int = 14, 45 NRWritePorts: Int = 8, 46 RoqSize: Int = 32, 47 IntDqDeqWidth: Int = 4, 48 FpDqDeqWidth: Int = 4, 49 LsDqDeqWidth: Int = 4, 50 dp1Paremeters: DP1Parameters = DP1Parameters( 51 IntDqSize = 16, 52 FpDqSize = 16, 53 LsDqSize = 16 54 ), 55 exuParameters: ExuParameters = ExuParameters( 56 JmpCnt = 1, 57 AluCnt = 4, 58 MulCnt = 1, 59 MduCnt = 1, 60 FmacCnt = 0, 61 FmiscCnt = 0, 62 FmiscDivSqrtCnt = 0, 63 LduCnt = 0, 64 StuCnt = 1 65 ) 66) 67 68 69trait HasXSParameter { 70 71 val core = Parameters.get.coreParameters 72 val env = Parameters.get.envParameters 73 74 val XLEN = core.XLEN 75 val HasMExtension = core.HasMExtension 76 val HasCExtension = core.HasCExtension 77 val HasDiv = core.HasDiv 78 val HasIcache = core.HasICache 79 val HasDcache = core.HasDCache 80 val EnableStoreQueue = core.EnableStoreQueue 81 val AddrBits = core.AddrBits // AddrBits is used in some cases 82 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 83 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 84 val AddrBytes = AddrBits / 8 // unused 85 val DataBits = XLEN 86 val DataBytes = DataBits / 8 87 val HasFPU = core.HasFPU 88 val FetchWidth = core.FectchWidth 89 val PredictWidth = FetchWidth * 2 90 val EnableBPU = core.EnableBPU 91 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 92 val EnableRAS = core.EnableRAS 93 val EnableLB = core.EnableLB 94 val HistoryLength = core.HistoryLength 95 val BtbSize = core.BtbSize 96 // val BtbWays = 4 97 val BtbBanks = PredictWidth 98 // val BtbSets = BtbSize / BtbWays 99 val JbtacSize = core.JbtacSize 100 val JbtacBanks = core.JbtacBanks 101 val RasSize = core.RasSize 102 val IBufSize = core.IBufSize 103 val DecodeWidth = core.DecodeWidth 104 val RenameWidth = core.RenameWidth 105 val CommitWidth = core.CommitWidth 106 val BrqSize = core.BrqSize 107 val IssQueSize = core.IssQueSize 108 val BrTagWidth = log2Up(BrqSize) 109 val NRPhyRegs = core.NRPhyRegs 110 val PhyRegIdxWidth = log2Up(NRPhyRegs) 111 val NRReadPorts = core.NRReadPorts 112 val NRWritePorts = core.NRWritePorts 113 val RoqSize = core.RoqSize 114 val InnerRoqIdxWidth = log2Up(RoqSize) 115 val RoqIdxWidth = InnerRoqIdxWidth + 1 116 val IntDqDeqWidth = core.IntDqDeqWidth 117 val FpDqDeqWidth = core.FpDqDeqWidth 118 val LsDqDeqWidth = core.LsDqDeqWidth 119 val dp1Paremeters = core.dp1Paremeters 120 val exuParameters = core.exuParameters 121} 122 123trait HasXSLog { this: Module => 124 implicit val moduleName: String = this.name 125} 126 127abstract class XSModule extends Module 128 with HasXSParameter 129 with HasExceptionNO 130 with HasXSLog 131 132//remove this trait after impl module logic 133trait NeedImpl { this: Module => 134 override protected def IO[T <: Data](iodef: T): T = { 135 val io = chisel3.experimental.IO(iodef) 136 io <> DontCare 137 io 138 } 139} 140 141abstract class XSBundle extends Bundle 142 with HasXSParameter 143 with HasTageParameter 144 145case class EnviromentParameters 146( 147 FPGAPlatform: Boolean = true, 148 EnableDebug: Boolean = false 149) 150 151object AddressSpace extends HasXSParameter { 152 // (start, size) 153 // address out of MMIO will be considered as DRAM 154 def mmio = List( 155 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 156 (0x40000000L, 0x40000000L) // external devices 157 ) 158 159 def isMMIO(addr: UInt): Bool = mmio.map(range => { 160 require(isPow2(range._2)) 161 val bits = log2Up(range._2) 162 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 163 }).reduce(_ || _) 164} 165 166 167class XSCore extends XSModule { 168 val io = IO(new Bundle { 169 val imem = new SimpleBusC 170 val dmem = new SimpleBusC 171 val mmio = new SimpleBusUC 172 val frontend = Flipped(new SimpleBusUC()) 173 }) 174 175 io.imem <> DontCare 176 177 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 178 179 val front = Module(new Frontend) 180 val backend = Module(new Backend) 181 182 front.io.backend <> backend.io.frontend 183 184 backend.io.memMMU.imem <> DontCare 185 186 val dtlb = TLB( 187 in = backend.io.dmem, 188 mem = dmemXbar.io.in(1), 189 flush = false.B, 190 csrMMU = backend.io.memMMU.dmem 191 )(TLBConfig(name = "dtlb", totalEntry = 64)) 192 dmemXbar.io.in(0) <> dtlb.io.out 193 dmemXbar.io.in(2) <> io.frontend 194 195 io.dmem <> Cache( 196 in = dmemXbar.io.out, 197 mmio = Seq(io.mmio), 198 flush = "b00".U, 199 empty = dtlb.io.cacheEmpty, 200 enable = HasDcache 201 )(CacheConfig(name = "dcache")) 202 203 XSDebug("(req valid, ready | resp valid, ready) \n") 204 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 205 io.dmem.mem.req.valid, 206 io.dmem.mem.req.ready, 207 io.dmem.mem.req.bits.addr, 208 io.dmem.mem.resp.valid, 209 io.dmem.mem.resp.ready, 210 io.dmem.coh.req.valid, 211 io.dmem.coh.req.ready, 212 io.dmem.coh.req.bits.addr, 213 io.dmem.coh.resp.valid, 214 io.dmem.coh.resp.ready, 215 dmemXbar.io.out.req.valid, 216 dmemXbar.io.out.req.ready, 217 dmemXbar.io.out.req.bits.addr, 218 dmemXbar.io.out.resp.valid, 219 dmemXbar.io.out.resp.ready, 220 backend.io.dmem.req.valid, 221 backend.io.dmem.req.ready, 222 backend.io.dmem.req.bits.addr, 223 backend.io.dmem.resp.valid, 224 backend.io.dmem.resp.ready 225 ) 226} 227