1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 21import freechips.rocketchip.tile.HasFPUParameters 22import utils._ 23 24case class XSCoreParameters 25( 26 XLEN: Int = 64, 27 HasMExtension: Boolean = true, 28 HasCExtension: Boolean = true, 29 HasDiv: Boolean = true, 30 HasICache: Boolean = true, 31 HasDCache: Boolean = true, 32 EnableStoreQueue: Boolean = true, 33 AddrBits: Int = 64, 34 VAddrBits: Int = 39, 35 PAddrBits: Int = 40, 36 HasFPU: Boolean = true, 37 FectchWidth: Int = 8, 38 EnableBPU: Boolean = true, 39 EnableBPD: Boolean = true, 40 EnableRAS: Boolean = true, 41 EnableLB: Boolean = false, 42 EnableLoop: Boolean = true, 43 EnableSC: Boolean = false, 44 HistoryLength: Int = 64, 45 BtbSize: Int = 2048, 46 JbtacSize: Int = 1024, 47 JbtacBanks: Int = 8, 48 RasSize: Int = 16, 49 CacheLineSize: Int = 512, 50 UBtbWays: Int = 16, 51 BtbWays: Int = 2, 52 53 EnableL1plusPrefetcher: Boolean = true, 54 IBufSize: Int = 32, 55 DecodeWidth: Int = 6, 56 RenameWidth: Int = 6, 57 CommitWidth: Int = 6, 58 BrqSize: Int = 32, 59 IssQueSize: Int = 12, 60 NRPhyRegs: Int = 160, 61 NRIntReadPorts: Int = 14, 62 NRIntWritePorts: Int = 8, 63 NRFpReadPorts: Int = 14, 64 NRFpWritePorts: Int = 8, 65 LoadQueueSize: Int = 64, 66 StoreQueueSize: Int = 48, 67 RoqSize: Int = 192, 68 dpParams: DispatchParameters = DispatchParameters( 69 IntDqSize = 32, 70 FpDqSize = 32, 71 LsDqSize = 32, 72 IntDqDeqWidth = 4, 73 FpDqDeqWidth = 4, 74 LsDqDeqWidth = 4 75 ), 76 exuParameters: ExuParameters = ExuParameters( 77 JmpCnt = 1, 78 AluCnt = 4, 79 MulCnt = 0, 80 MduCnt = 2, 81 FmacCnt = 4, 82 FmiscCnt = 2, 83 FmiscDivSqrtCnt = 0, 84 LduCnt = 2, 85 StuCnt = 2 86 ), 87 LoadPipelineWidth: Int = 2, 88 StorePipelineWidth: Int = 2, 89 StoreBufferSize: Int = 16, 90 RefillSize: Int = 512, 91 TlbEntrySize: Int = 32, 92 TlbSPEntrySize: Int = 4, 93 TlbL2EntrySize: Int = 256, // or 512 94 TlbL2SPEntrySize: Int = 16, 95 PtwL1EntrySize: Int = 16, 96 PtwL2EntrySize: Int = 256, 97 NumPerfCounters: Int = 16, 98 NrExtIntr: Int = 1 99) 100 101trait HasXSParameter { 102 103 val core = Parameters.get.coreParameters 104 val env = Parameters.get.envParameters 105 106 val XLEN = 64 107 val minFLen = 32 108 val fLen = 64 109 def xLen = 64 110 val HasMExtension = core.HasMExtension 111 val HasCExtension = core.HasCExtension 112 val HasDiv = core.HasDiv 113 val HasIcache = core.HasICache 114 val HasDcache = core.HasDCache 115 val EnableStoreQueue = core.EnableStoreQueue 116 val AddrBits = core.AddrBits // AddrBits is used in some cases 117 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 118 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 119 val AddrBytes = AddrBits / 8 // unused 120 val DataBits = XLEN 121 val DataBytes = DataBits / 8 122 val HasFPU = core.HasFPU 123 val FetchWidth = core.FectchWidth 124 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 125 val EnableBPU = core.EnableBPU 126 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 127 val EnableRAS = core.EnableRAS 128 val EnableLB = core.EnableLB 129 val EnableLoop = core.EnableLoop 130 val EnableSC = core.EnableSC 131 val HistoryLength = core.HistoryLength 132 val BtbSize = core.BtbSize 133 // val BtbWays = 4 134 val BtbBanks = PredictWidth 135 // val BtbSets = BtbSize / BtbWays 136 val JbtacSize = core.JbtacSize 137 val JbtacBanks = core.JbtacBanks 138 val RasSize = core.RasSize 139 val CacheLineSize = core.CacheLineSize 140 val CacheLineHalfWord = CacheLineSize / 16 141 val ExtHistoryLength = HistoryLength + 64 142 val UBtbWays = core.UBtbWays 143 val BtbWays = core.BtbWays 144 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 145 val IBufSize = core.IBufSize 146 val DecodeWidth = core.DecodeWidth 147 val RenameWidth = core.RenameWidth 148 val CommitWidth = core.CommitWidth 149 val BrqSize = core.BrqSize 150 val IssQueSize = core.IssQueSize 151 val BrTagWidth = log2Up(BrqSize) 152 val NRPhyRegs = core.NRPhyRegs 153 val PhyRegIdxWidth = log2Up(NRPhyRegs) 154 val RoqSize = core.RoqSize 155 val LoadQueueSize = core.LoadQueueSize 156 val StoreQueueSize = core.StoreQueueSize 157 val dpParams = core.dpParams 158 val exuParameters = core.exuParameters 159 val NRIntReadPorts = core.NRIntReadPorts 160 val NRIntWritePorts = core.NRIntWritePorts 161 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 162 val NRFpReadPorts = core.NRFpReadPorts 163 val NRFpWritePorts = core.NRFpWritePorts 164 val LoadPipelineWidth = core.LoadPipelineWidth 165 val StorePipelineWidth = core.StorePipelineWidth 166 val StoreBufferSize = core.StoreBufferSize 167 val RefillSize = core.RefillSize 168 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 169 val TlbEntrySize = core.TlbEntrySize 170 val TlbSPEntrySize = core.TlbSPEntrySize 171 val TlbL2EntrySize = core.TlbL2EntrySize 172 val TlbL2SPEntrySize = core.TlbL2SPEntrySize 173 val PtwL1EntrySize = core.PtwL1EntrySize 174 val PtwL2EntrySize = core.PtwL2EntrySize 175 val NumPerfCounters = core.NumPerfCounters 176 val NrExtIntr = core.NrExtIntr 177 178 val icacheParameters = ICacheParameters( 179 tagECC = Some("parity"), 180 dataECC = Some("parity"), 181 nMissEntries = 2 182 ) 183 184 val l1plusCacheParameters = L1plusCacheParameters( 185 tagECC = Some("secded"), 186 dataECC = Some("secded"), 187 nMissEntries = 8 188 ) 189 190 val dcacheParameters = DCacheParameters( 191 tagECC = Some("secded"), 192 dataECC = Some("secded"), 193 nMissEntries = 16, 194 nProbeEntries = 16, 195 nReleaseEntries = 16, 196 nStoreReplayEntries = 16 197 ) 198 199 val LRSCCycles = 100 200 201 202 // cache hierarchy configurations 203 val l1BusDataWidth = 256 204 205 // L2 configurations 206 val L1BusWidth = 256 207 val L2Size = 512 * 1024 // 512KB 208 val L2BlockSize = 64 209 val L2NWays = 8 210 val L2NSets = L2Size / L2BlockSize / L2NWays 211 212 // L3 configurations 213 val L2BusWidth = 256 214 val L3Size = 4 * 1024 * 1024 // 4MB 215 val L3BlockSize = 64 216 val L3NBanks = 4 217 val L3NWays = 8 218 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 219 220 // on chip network configurations 221 val L3BusWidth = 256 222 223 // icache prefetcher 224 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 225 enable = true, 226 _type = "stream", 227 streamParams = StreamPrefetchParameters( 228 streamCnt = 2, 229 streamSize = 4, 230 ageWidth = 4, 231 blockBytes = l1plusCacheParameters.blockBytes, 232 reallocStreamOnMissInstantly = true, 233 cacheName = "icache" 234 ) 235 ) 236 237 // dcache prefetcher 238 val l2PrefetcherParameters = L2PrefetcherParameters( 239 enable = true, 240 _type = "stream", 241 streamParams = StreamPrefetchParameters( 242 streamCnt = 4, 243 streamSize = 4, 244 ageWidth = 4, 245 blockBytes = L2BlockSize, 246 reallocStreamOnMissInstantly = true, 247 cacheName = "dcache" 248 ) 249 ) 250} 251 252trait HasXSLog { this: RawModule => 253 implicit val moduleName: String = this.name 254} 255 256abstract class XSModule extends MultiIOModule 257 with HasXSParameter 258 with HasExceptionNO 259 with HasXSLog 260 with HasFPUParameters 261{ 262 def io: Record 263} 264 265//remove this trait after impl module logic 266trait NeedImpl { this: RawModule => 267 override protected def IO[T <: Data](iodef: T): T = { 268 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 269 val io = chisel3.experimental.IO(iodef) 270 io <> DontCare 271 io 272 } 273} 274 275abstract class XSBundle extends Bundle 276 with HasXSParameter 277 278case class EnviromentParameters 279( 280 FPGAPlatform: Boolean = true, 281 EnableDebug: Boolean = false 282) 283 284// object AddressSpace extends HasXSParameter { 285// // (start, size) 286// // address out of MMIO will be considered as DRAM 287// def mmio = List( 288// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 289// (0x40000000L, 0x40000000L) // external devices 290// ) 291 292// def isMMIO(addr: UInt): Bool = mmio.map(range => { 293// require(isPow2(range._2)) 294// val bits = log2Up(range._2) 295// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 296// }).reduce(_ || _) 297// } 298 299 300 301class XSCore()(implicit p: config.Parameters) extends LazyModule 302 with HasXSParameter 303 with HasExeBlockHelper 304{ 305 306 // to fast wake up fp, mem rs 307 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 308 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 309 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 310 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 311 312 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 313 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 314 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 315 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 316 317 // outer facing nodes 318 val l1pluscache = LazyModule(new L1plusCache()) 319 val ptw = LazyModule(new PTW()) 320 val l2Prefetcher = LazyModule(new L2Prefetcher()) 321 val memBlock = LazyModule(new MemBlock( 322 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 323 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 324 fastFpOut = Seq(), 325 slowFpOut = loadExuConfigs, 326 fastIntOut = Seq(), 327 slowIntOut = loadExuConfigs 328 )) 329 330 lazy val module = new XSCoreImp(this) 331} 332 333class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 334 with HasXSParameter 335 with HasExeBlockHelper 336{ 337 val io = IO(new Bundle { 338 val externalInterrupt = new ExternalInterruptIO 339 }) 340 341 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 342 AddressSpace.printMemmap() 343 344 // to fast wake up fp, mem rs 345 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 346 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 347 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 348 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 349 350 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 351 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 352 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 353 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 354 355 val frontend = Module(new Frontend) 356 val ctrlBlock = Module(new CtrlBlock) 357 val integerBlock = Module(new IntegerBlock( 358 fastWakeUpIn = fpBlockFastWakeUpInt, 359 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 360 fastFpOut = intBlockFastWakeUpFp, 361 slowFpOut = intBlockSlowWakeUpFp, 362 fastIntOut = intBlockFastWakeUpInt, 363 slowIntOut = intBlockSlowWakeUpInt 364 )) 365 val floatBlock = Module(new FloatBlock( 366 fastWakeUpIn = intBlockFastWakeUpFp, 367 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 368 fastFpOut = fpBlockFastWakeUpFp, 369 slowFpOut = fpBlockSlowWakeUpFp, 370 fastIntOut = fpBlockFastWakeUpInt, 371 slowIntOut = fpBlockSlowWakeUpInt 372 )) 373 374 val memBlock = outer.memBlock.module 375 val l1pluscache = outer.l1pluscache.module 376 val ptw = outer.ptw.module 377 val l2Prefetcher = outer.l2Prefetcher.module 378 379 frontend.io.backend <> ctrlBlock.io.frontend 380 frontend.io.sfence <> integerBlock.io.fenceio.sfence 381 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 382 383 frontend.io.icacheMemAcq <> l1pluscache.io.req 384 l1pluscache.io.resp <> frontend.io.icacheMemGrant 385 l1pluscache.io.flush := frontend.io.l1plusFlush 386 frontend.io.fencei := integerBlock.io.fenceio.fencei 387 388 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 389 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 390 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 391 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 392 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 393 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 394 395 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 396 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 397 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 398 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 399 400 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 401 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 402 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 403 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 404 405 406 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 407 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 408 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 409 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 410 411 val wakeUpMem = Seq( 412 integerBlock.io.wakeUpIntOut, 413 integerBlock.io.wakeUpFpOut, 414 floatBlock.io.wakeUpIntOut, 415 floatBlock.io.wakeUpFpOut 416 ) 417 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 418 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 419 val raw = WireInit(f) 420 raw 421 })) 422 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 423 val raw = WireInit(s) 424 raw 425 })) 426 427 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 428 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 429 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 430 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 431 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 432 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 433 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 434 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 435 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 436 integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo 437 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 438 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 439 440 floatBlock.io.frm <> integerBlock.io.csrio.frm 441 442 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 443 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 444 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 445 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 446 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 447 448 ptw.io.tlb(0) <> memBlock.io.ptw 449 ptw.io.tlb(1) <> frontend.io.ptw 450 ptw.io.sfence <> integerBlock.io.fenceio.sfence 451 ptw.io.csr <> integerBlock.io.csrio.tlb 452 453 l2Prefetcher.io.in <> memBlock.io.toDCachePrefetch 454 455 if (!env.FPGAPlatform) { 456 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 457 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 458 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 459 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 460 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 461 } 462 463} 464