1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utility._ 28import utils._ 29import xiangshan.backend._ 30import xiangshan.cache.mmu._ 31import xiangshan.frontend._ 32import xiangshan.mem.L1PrefetchFuzzer 33 34abstract class XSModule(implicit val p: Parameters) extends Module 35 with HasXSParameter 36 with HasFPUParameters 37 38//remove this trait after impl module logic 39trait NeedImpl { 40 this: RawModule => 41 override protected def IO[T <: Data](iodef: T): T = { 42 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 43 val io = chisel3.experimental.IO(iodef) 44 io <> DontCare 45 io 46 } 47} 48 49abstract class XSBundle(implicit val p: Parameters) extends Bundle 50 with HasXSParameter 51 52abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 53 with HasXSParameter 54{ 55 // interrupt sinks 56 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 57 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 58 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 59 // outer facing nodes 60 val frontend = LazyModule(new Frontend()) 61 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 62 val backend = LazyModule(new Backend(backendParams)) 63 64 val memBlock = LazyModule(new MemBlock) 65} 66 67class XSCore()(implicit p: config.Parameters) extends XSCoreBase 68 with HasXSDts 69{ 70 lazy val module = new XSCoreImp(this) 71} 72 73class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 74 with HasXSParameter 75 with HasSoCParameter { 76 val io = IO(new Bundle { 77 val hartId = Input(UInt(64.W)) 78 val reset_vector = Input(UInt(PAddrBits.W)) 79 val cpu_halt = Output(Bool()) 80 val l2_pf_enable = Output(Bool()) 81 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 82 val beu_errors = Output(new XSL1BusErrors()) 83 val l2_hint = Input(Valid(new L2ToL1Hint())) 84 }) 85 86 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 87 88 val frontend = outer.frontend.module 89 val backend = outer.backend.module 90 val memBlock = outer.memBlock.module 91 92 val fenceio = backend.io.fenceio 93 fenceio.disableSfence := DontCare 94 95 frontend.io.hartId := io.hartId 96 frontend.io.backend <> backend.io.frontend 97 frontend.io.sfence <> backend.io.frontendSfence 98 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 99 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 100 frontend.io.fencei <> fenceio.fencei 101 102 backend.io.fromTop.hartId := io.hartId 103 backend.io.fromTop.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 104 backend.io.fromTop.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 105 backend.io.fromTop.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 106 backend.io.fromTop.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 107 backend.io.fromTop.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 108 109 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 110 111 backend.io.mem.stIn.zip(memBlock.io.stIn).foreach { case (sink, source) => 112 sink.valid := source.valid 113 sink.bits := 0.U.asTypeOf(sink.bits) 114 sink.bits.robIdx := source.bits.uop.robIdx 115 sink.bits.ssid := source.bits.uop.ssid 116 sink.bits.storeSetHit := source.bits.uop.storeSetHit 117 // The other signals have not been used 118 } 119 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 120 backend.io.mem.lsqEnqIO <> memBlock.io.enqLsq 121 backend.io.mem.sqDeq := memBlock.io.sqDeq 122 backend.io.mem.lqDeq := memBlock.io.lqDeq 123 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 124 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 125 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 126 backend.io.mem.stIssuePtr := memBlock.io.stIssuePtr 127 backend.io.mem.ldaIqFeedback <> memBlock.io.ldaIqFeedback 128 backend.io.mem.staIqFeedback <> memBlock.io.staIqFeedback 129 backend.io.mem.ldCancel <> memBlock.io.ldCancel 130 backend.io.mem.writeBack.zipAll(memBlock.io.writeback, DontCare, DontCare).foreach { case (back, mem) => 131 back <> mem 132 } // TODO: replace zipAll with zip when vls is fully implemented 133 134 frontend.io.reset_vector := io.reset_vector 135 136 io.cpu_halt := backend.io.toTop.cpuHalted 137 138 // memblock error exception writeback, 1 cycle after normal writeback 139 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 140 141 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 142 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 143 144 memBlock.io.hartId := io.hartId 145 memBlock.io.issue.zipAll(backend.io.mem.issueUops, DontCare, DontCare).foreach { case(memIssue, backIssue) => 146 backIssue <> memIssue 147 } // TODO: replace zipAll with zip when vls is fully implemented 148 // By default, instructions do not have exceptions when they enter the function units. 149 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 150 memBlock.io.loadPc := backend.io.mem.loadPcRead 151 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 152 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 153 backend.io.mem.exceptionVAddr := memBlock.io.lsqio.exceptionAddr.vaddr 154 backend.io.mem.csrDistributedUpdate := memBlock.io.csrUpdate 155 backend.io.mem.debugLS := memBlock.io.debug_ls 156 backend.io.mem.lsTopdownInfo := memBlock.io.lsTopdownInfo 157 backend.io.mem.lqCanAccept := memBlock.io.lsqio.lqCanAccept 158 backend.io.mem.sqCanAccept := memBlock.io.lsqio.sqCanAccept 159 160 backend.io.perf.frontendInfo := frontend.io.frontendInfo 161 backend.io.perf.memInfo := memBlock.io.memInfo 162 backend.io.perf.perfEventsFrontend := frontend.getPerf 163 backend.io.perf.perfEventsLsu := memBlock.getPerf 164 backend.io.perf.perfEventsHc := io.perfEvents 165 backend.io.perf.perfEventsCtrl := DontCare 166 backend.io.perf.retiredInstr := DontCare 167 backend.io.perf.ctrlInfo := DontCare 168 169 memBlock.io.sfence <> backend.io.mem.sfence 170 memBlock.io.fenceToSbuffer <> backend.io.fenceio.sbuffer 171 172 memBlock.io.redirect <> backend.io.mem.redirect 173 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 174 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 175 memBlock.io.lsqio.rob <> backend.io.mem.robLsqIO 176 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 177 memBlock.io.itlb <> frontend.io.ptw 178 memBlock.io.l2_hint.valid := io.l2_hint.valid 179 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 180 181 // TODO: Connect us when implemented 182 memBlock.io.int2vlsu <> DontCare 183 memBlock.io.vec2vlsu <> DontCare 184 memBlock.io.vlsu2vec <> DontCare 185 memBlock.io.vlsu2int <> DontCare 186 memBlock.io.vlsu2ctrl <> DontCare 187 188 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 189 io.l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 190 191 // Modules are reset one by one 192 val resetTree = ResetGenNode( 193 Seq( 194 ModuleNode(memBlock), 195 ResetGenNode(Seq( 196 ModuleNode(backend), 197 ResetGenNode(Seq( 198 ResetGenNode(Seq( 199 ModuleNode(frontend) 200 )) 201 )) 202 )) 203 ) 204 ) 205 206 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 207 208} 209