xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 6886802ea3b46474a67fef08bfd8fcb54251fc7d) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import top.Parameters
6import xiangshan.backend._
7import xiangshan.backend.dispatch.DispatchParameters
8import xiangshan.backend.exu.ExuParameters
9import xiangshan.backend.exu.Exu._
10import xiangshan.frontend._
11import xiangshan.mem._
12import xiangshan.backend.fu.HasExceptionNO
13import xiangshan.cache.{DCache,InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache, MemoryOpConstants, MissReq}
14import xiangshan.cache.prefetch._
15import chipsalliance.rocketchip.config
16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar}
18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker}
21import freechips.rocketchip.tile.HasFPUParameters
22import sifive.blocks.inclusivecache.PrefetcherIO
23import utils._
24
25object hartIdCore extends (() => Int) {
26  var x = 0
27  def apply(): Int = {
28    x = x + 1
29    x-1
30  }
31}
32
33case class XSCoreParameters
34(
35  XLEN: Int = 64,
36  HasMExtension: Boolean = true,
37  HasCExtension: Boolean = true,
38  HasDiv: Boolean = true,
39  HasICache: Boolean = true,
40  HasDCache: Boolean = true,
41  EnableStoreQueue: Boolean = true,
42  AddrBits: Int = 64,
43  VAddrBits: Int = 39,
44  PAddrBits: Int = 40,
45  HasFPU: Boolean = true,
46  FectchWidth: Int = 8,
47  EnableBPU: Boolean = true,
48  EnableBPD: Boolean = true,
49  EnableRAS: Boolean = true,
50  EnableLB: Boolean = false,
51  EnableLoop: Boolean = false,
52  EnableSC: Boolean = false,
53  EnableJal: Boolean = false,
54  EnableUBTB: Boolean = true,
55  HistoryLength: Int = 64,
56  BtbSize: Int = 2048,
57  JbtacSize: Int = 1024,
58  JbtacBanks: Int = 8,
59  RasSize: Int = 16,
60  CacheLineSize: Int = 512,
61  UBtbWays: Int = 16,
62  BtbWays: Int = 2,
63
64  EnableL1plusPrefetcher: Boolean = true,
65  IBufSize: Int = 32,
66  DecodeWidth: Int = 6,
67  RenameWidth: Int = 6,
68  CommitWidth: Int = 6,
69  BrqSize: Int = 32,
70  FtqSize: Int = 48,
71  IssQueSize: Int = 12,
72  NRPhyRegs: Int = 160,
73  NRIntReadPorts: Int = 14,
74  NRIntWritePorts: Int = 8,
75  NRFpReadPorts: Int = 14,
76  NRFpWritePorts: Int = 8,
77  LoadQueueSize: Int = 64,
78  StoreQueueSize: Int = 48,
79  RoqSize: Int = 192,
80  dpParams: DispatchParameters = DispatchParameters(
81    IntDqSize = 32,
82    FpDqSize = 32,
83    LsDqSize = 32,
84    IntDqDeqWidth = 4,
85    FpDqDeqWidth = 4,
86    LsDqDeqWidth = 4
87  ),
88  exuParameters: ExuParameters = ExuParameters(
89    JmpCnt = 1,
90    AluCnt = 4,
91    MulCnt = 0,
92    MduCnt = 2,
93    FmacCnt = 4,
94    FmiscCnt = 2,
95    FmiscDivSqrtCnt = 0,
96    LduCnt = 2,
97    StuCnt = 2
98  ),
99  LoadPipelineWidth: Int = 2,
100  StorePipelineWidth: Int = 2,
101  StoreBufferSize: Int = 16,
102  RefillSize: Int = 512,
103  TlbEntrySize: Int = 32,
104  TlbSPEntrySize: Int = 4,
105  TlbL2EntrySize: Int = 256, // or 512
106  TlbL2SPEntrySize: Int = 16,
107  PtwL1EntrySize: Int = 16,
108  PtwL2EntrySize: Int = 256,
109  NumPerfCounters: Int = 16,
110  NrExtIntr: Int = 1
111)
112
113trait HasXSParameter {
114
115  val core = Parameters.get.coreParameters
116  val env = Parameters.get.envParameters
117
118  val XLEN = 64
119  val minFLen = 32
120  val fLen = 64
121  def xLen = 64
122  val HasMExtension = core.HasMExtension
123  val HasCExtension = core.HasCExtension
124  val HasDiv = core.HasDiv
125  val HasIcache = core.HasICache
126  val HasDcache = core.HasDCache
127  val EnableStoreQueue = core.EnableStoreQueue
128  val AddrBits = core.AddrBits // AddrBits is used in some cases
129  val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits
130  val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits
131  val AddrBytes = AddrBits / 8 // unused
132  val DataBits = XLEN
133  val DataBytes = DataBits / 8
134  val HasFPU = core.HasFPU
135  val FetchWidth = core.FectchWidth
136  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
137  val EnableBPU = core.EnableBPU
138  val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3
139  val EnableRAS = core.EnableRAS
140  val EnableLB = core.EnableLB
141  val EnableLoop = core.EnableLoop
142  val EnableSC = core.EnableSC
143  val HistoryLength = core.HistoryLength
144  val BtbSize = core.BtbSize
145  // val BtbWays = 4
146  val BtbBanks = PredictWidth
147  // val BtbSets = BtbSize / BtbWays
148  val JbtacSize = core.JbtacSize
149  val JbtacBanks = core.JbtacBanks
150  val RasSize = core.RasSize
151  val CacheLineSize = core.CacheLineSize
152  val CacheLineHalfWord = CacheLineSize / 16
153  val ExtHistoryLength = HistoryLength + 64
154  val UBtbWays = core.UBtbWays
155  val BtbWays = core.BtbWays
156  val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher
157  val IBufSize = core.IBufSize
158  val DecodeWidth = core.DecodeWidth
159  val RenameWidth = core.RenameWidth
160  val CommitWidth = core.CommitWidth
161  val BrqSize = core.BrqSize
162  val FtqSize = core.FtqSize
163  val IssQueSize = core.IssQueSize
164  val BrTagWidth = log2Up(BrqSize)
165  val NRPhyRegs = core.NRPhyRegs
166  val PhyRegIdxWidth = log2Up(NRPhyRegs)
167  val RoqSize = core.RoqSize
168  val LoadQueueSize = core.LoadQueueSize
169  val StoreQueueSize = core.StoreQueueSize
170  val dpParams = core.dpParams
171  val exuParameters = core.exuParameters
172  val NRIntReadPorts = core.NRIntReadPorts
173  val NRIntWritePorts = core.NRIntWritePorts
174  val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt
175  val NRFpReadPorts = core.NRFpReadPorts
176  val NRFpWritePorts = core.NRFpWritePorts
177  val LoadPipelineWidth = core.LoadPipelineWidth
178  val StorePipelineWidth = core.StorePipelineWidth
179  val StoreBufferSize = core.StoreBufferSize
180  val RefillSize = core.RefillSize
181  val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth
182  val TlbEntrySize = core.TlbEntrySize
183  val TlbSPEntrySize = core.TlbSPEntrySize
184  val TlbL2EntrySize = core.TlbL2EntrySize
185  val TlbL2SPEntrySize = core.TlbL2SPEntrySize
186  val PtwL1EntrySize = core.PtwL1EntrySize
187  val PtwL2EntrySize = core.PtwL2EntrySize
188  val NumPerfCounters = core.NumPerfCounters
189  val NrExtIntr = core.NrExtIntr
190
191  val instBytes = if (HasCExtension) 2 else 4
192  val instOffsetBits = log2Ceil(instBytes)
193
194  val icacheParameters = ICacheParameters(
195    tagECC = Some("parity"),
196    dataECC = Some("parity"),
197    nMissEntries = 2
198  )
199
200  val l1plusCacheParameters = L1plusCacheParameters(
201    tagECC = Some("secded"),
202    dataECC = Some("secded"),
203    nMissEntries = 8
204  )
205
206  val dcacheParameters = DCacheParameters(
207    tagECC = Some("secded"),
208    dataECC = Some("secded"),
209    nMissEntries = 16,
210    nLoadMissEntries = 8,
211    nStoreMissEntries = 8
212  )
213
214  val LRSCCycles = 100
215
216
217  // cache hierarchy configurations
218  val l1BusDataWidth = 256
219
220  // L2 configurations
221  val L1BusWidth = 256
222  val L2Size = 512 * 1024 // 512KB
223  val L2BlockSize = 64
224  val L2NWays = 8
225  val L2NSets = L2Size / L2BlockSize / L2NWays
226
227  // L3 configurations
228  val L2BusWidth = 256
229  val L3Size = 4 * 1024 * 1024 // 4MB
230  val L3BlockSize = 64
231  val L3NBanks = 4
232  val L3NWays = 8
233  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
234
235  // on chip network configurations
236  val L3BusWidth = 256
237
238  // icache prefetcher
239  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
240    enable = true,
241    _type = "stream",
242    streamParams = StreamPrefetchParameters(
243      streamCnt = 2,
244      streamSize = 4,
245      ageWidth = 4,
246      blockBytes = l1plusCacheParameters.blockBytes,
247      reallocStreamOnMissInstantly = true,
248      cacheName = "icache"
249    )
250  )
251
252  // dcache prefetcher
253  val l2PrefetcherParameters = L2PrefetcherParameters(
254    enable = true,
255    _type = "bop",// "stream" or "bop"
256    streamParams = StreamPrefetchParameters(
257      streamCnt = 4,
258      streamSize = 4,
259      ageWidth = 4,
260      blockBytes = L2BlockSize,
261      reallocStreamOnMissInstantly = true,
262      cacheName = "dcache"
263    ),
264    bopParams = BOPParameters(
265      rrTableEntries = 256,
266      rrTagBits = 12,
267      scoreBits = 5,
268      roundMax = 50,
269      badScore = 1,
270      blockBytes = L2BlockSize,
271      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
272    ),
273  )
274}
275
276trait HasXSLog { this: RawModule =>
277  implicit val moduleName: String = this.name
278}
279
280abstract class XSModule extends MultiIOModule
281  with HasXSParameter
282  with HasExceptionNO
283  with HasXSLog
284  with HasFPUParameters
285{
286  def io: Record
287}
288
289//remove this trait after impl module logic
290trait NeedImpl { this: RawModule =>
291  override protected def IO[T <: Data](iodef: T): T = {
292    println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module")
293    val io = chisel3.experimental.IO(iodef)
294    io <> DontCare
295    io
296  }
297}
298
299abstract class XSBundle extends Bundle
300  with HasXSParameter
301
302case class EnviromentParameters
303(
304  FPGAPlatform: Boolean = true,
305  EnableDebug: Boolean = false,
306  EnablePerfDebug: Boolean = false,
307  DualCoreDifftest: Boolean = false
308)
309
310// object AddressSpace extends HasXSParameter {
311//   // (start, size)
312//   // address out of MMIO will be considered as DRAM
313//   def mmio = List(
314//     (0x00000000L, 0x40000000L),  // internal devices, such as CLINT and PLIC
315//     (0x40000000L, 0x40000000L)   // external devices
316//   )
317
318//   def isMMIO(addr: UInt): Bool = mmio.map(range => {
319//     require(isPow2(range._2))
320//     val bits = log2Up(range._2)
321//     (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
322//   }).reduce(_ || _)
323// }
324
325
326
327class XSCore()(implicit p: config.Parameters) extends LazyModule
328  with HasXSParameter
329  with HasExeBlockHelper
330{
331
332  // to fast wake up fp, mem rs
333  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
334  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
335  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
336  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
337
338  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
339  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
340  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
341  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
342
343  // outer facing nodes
344  val frontend = LazyModule(new Frontend())
345  val l1pluscache = LazyModule(new L1plusCache())
346  val ptw = LazyModule(new PTW())
347  val l2Prefetcher = LazyModule(new L2Prefetcher())
348  val memBlock = LazyModule(new MemBlock(
349    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
350    slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
351    fastFpOut = Seq(),
352    slowFpOut = loadExuConfigs,
353    fastIntOut = Seq(),
354    slowIntOut = loadExuConfigs
355  ))
356
357  lazy val module = new XSCoreImp(this)
358}
359
360class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
361  with HasXSParameter
362  with HasExeBlockHelper
363{
364  val io = IO(new Bundle {
365    val externalInterrupt = new ExternalInterruptIO
366    val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits))
367  })
368  val difftestIO = IO(new DifftestBundle())
369  difftestIO <> DontCare
370
371  println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
372  AddressSpace.printMemmap()
373
374  // to fast wake up fp, mem rs
375  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
376  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
377  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
378  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
379
380  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
381  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
382  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
383  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
384
385  val ctrlBlock = Module(new CtrlBlock)
386  val integerBlock = Module(new IntegerBlock(
387    fastWakeUpIn = fpBlockFastWakeUpInt,
388    slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs,
389    fastFpOut = intBlockFastWakeUpFp,
390    slowFpOut = intBlockSlowWakeUpFp,
391    fastIntOut = intBlockFastWakeUpInt,
392    slowIntOut = intBlockSlowWakeUpInt
393  ))
394  val floatBlock = Module(new FloatBlock(
395    fastWakeUpIn = intBlockFastWakeUpFp,
396    slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs,
397    fastFpOut = fpBlockFastWakeUpFp,
398    slowFpOut = fpBlockSlowWakeUpFp,
399    fastIntOut = fpBlockFastWakeUpInt,
400    slowIntOut = fpBlockSlowWakeUpInt
401  ))
402
403  val frontend = outer.frontend.module
404  val memBlock = outer.memBlock.module
405  val l1pluscache = outer.l1pluscache.module
406  val ptw = outer.ptw.module
407  val l2Prefetcher = outer.l2Prefetcher.module
408
409  frontend.io.backend <> ctrlBlock.io.frontend
410  frontend.io.sfence <> integerBlock.io.fenceio.sfence
411  frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
412
413  frontend.io.icacheMemAcq <> l1pluscache.io.req
414  l1pluscache.io.resp <> frontend.io.icacheMemGrant
415  l1pluscache.io.flush := frontend.io.l1plusFlush
416  frontend.io.fencei := integerBlock.io.fenceio.fencei
417
418  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
419  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
420  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
421  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
422  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
423  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
424
425  integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops
426  integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast
427  integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow
428  integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
429
430  floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops
431  floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast
432  floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow
433  floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
434
435
436  integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B)
437  integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B)
438  floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B)
439  floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B)
440
441  val wakeUpMem = Seq(
442    integerBlock.io.wakeUpIntOut,
443    integerBlock.io.wakeUpFpOut,
444    floatBlock.io.wakeUpIntOut,
445    floatBlock.io.wakeUpFpOut
446  )
447  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
448  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => {
449	val raw = WireInit(f)
450	raw
451  }))
452  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => {
453	val raw = WireInit(s)
454	raw
455  }))
456
457  integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags
458  integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
459  integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
460  integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt
461  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
462  integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
463  integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
464  integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
465  integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr
466  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
467  integerBlock.io.fenceio.sfence <> memBlock.io.sfence
468  integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
469
470  floatBlock.io.frm <> integerBlock.io.csrio.frm
471
472  memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits
473  memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr
474  memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx
475  memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx
476  memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType)
477
478  ptw.io.tlb(0) <> memBlock.io.ptw
479  ptw.io.tlb(1) <> frontend.io.ptw
480  ptw.io.sfence <> integerBlock.io.fenceio.sfence
481  ptw.io.csr    <> integerBlock.io.csrio.tlb
482
483  val l2PrefetcherIn = Wire(Decoupled(new MissReq))
484  if (l2PrefetcherParameters.enable && l2PrefetcherParameters._type == "bop") {
485    l2PrefetcherIn.valid := io.l2ToPrefetcher.acquire.valid
486    l2PrefetcherIn.bits := DontCare
487    l2PrefetcherIn.bits.addr := io.l2ToPrefetcher.acquire.bits.address
488    l2PrefetcherIn.bits.cmd := Mux(io.l2ToPrefetcher.acquire.bits.write, MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD)
489  } else {
490    l2PrefetcherIn <> memBlock.io.toDCachePrefetch
491  }
492  l2Prefetcher.io.in <> l2PrefetcherIn
493
494  if (!env.FPGAPlatform) {
495    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
496    ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug)
497    ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug)
498    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
499    ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug)
500  }
501
502  if (env.DualCoreDifftest) {
503    val id = hartIdCore()
504    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
505    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
506    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
507    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
508
509    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
510    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
511    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
512    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
513    difftestIO.fromXSCore.r := debugArchReg
514  }
515
516}
517