1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import xiangshan.mem._ 13import utils._ 14import xiangshan.cache.DcacheUserBundle 15 16case class XSCoreParameters 17( 18 XLEN: Int = 64, 19 HasMExtension: Boolean = true, 20 HasCExtension: Boolean = true, 21 HasDiv: Boolean = true, 22 HasICache: Boolean = true, 23 HasDCache: Boolean = true, 24 EnableStoreQueue: Boolean = true, 25 AddrBits: Int = 64, 26 VAddrBits: Int = 39, 27 PAddrBits: Int = 32, 28 HasFPU: Boolean = true, 29 FectchWidth: Int = 8, 30 EnableBPU: Boolean = true, 31 EnableBPD: Boolean = false, 32 EnableRAS: Boolean = false, 33 EnableLB: Boolean = false, 34 HistoryLength: Int = 64, 35 BtbSize: Int = 256, 36 JbtacSize: Int = 1024, 37 JbtacBanks: Int = 8, 38 RasSize: Int = 16, 39 CacheLineSize: Int = 512, 40 UBtbWays: Int = 16, 41 BtbWays: Int = 2, 42 IBufSize: Int = 64, 43 DecodeWidth: Int = 6, 44 RenameWidth: Int = 6, 45 CommitWidth: Int = 6, 46 BrqSize: Int = 16, 47 IssQueSize: Int = 8, 48 NRPhyRegs: Int = 128, 49 NRIntReadPorts: Int = 8, 50 NRIntWritePorts: Int = 8, 51 NRFpReadPorts: Int = 14, 52 NRFpWritePorts: Int = 8, 53 LsroqSize: Int = 16, 54 RoqSize: Int = 32, 55 IntDqDeqWidth: Int = 4, 56 FpDqDeqWidth: Int = 4, 57 LsDqDeqWidth: Int = 4, 58 ReplayWidth: Int = 8, 59 dpParams: DispatchParameters = DispatchParameters( 60 DqEnqWidth = 4, 61 IntDqSize = 64, 62 FpDqSize = 64, 63 LsDqSize = 64, 64 IntDqDeqWidth = 4, 65 FpDqDeqWidth = 4, 66 LsDqDeqWidth = 4 67 ), 68 exuParameters: ExuParameters = ExuParameters( 69 JmpCnt = 1, 70 AluCnt = 4, 71 MulCnt = 0, 72 MduCnt = 2, 73 FmacCnt = 0, 74 FmiscCnt = 0, 75 FmiscDivSqrtCnt = 0, 76 LduCnt = 2, 77 StuCnt = 2 78 ), 79 LoadPipelineWidth: Int = 2, 80 StorePipelineWidth: Int = 2, 81 StoreBufferSize: Int = 16, 82 RefillSize: Int = 512 83) 84 85 86trait HasXSParameter { 87 88 val core = Parameters.get.coreParameters 89 val env = Parameters.get.envParameters 90 91 val XLEN = core.XLEN 92 val HasMExtension = core.HasMExtension 93 val HasCExtension = core.HasCExtension 94 val HasDiv = core.HasDiv 95 val HasIcache = core.HasICache 96 val HasDcache = core.HasDCache 97 val EnableStoreQueue = core.EnableStoreQueue 98 val AddrBits = core.AddrBits // AddrBits is used in some cases 99 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 100 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 101 val AddrBytes = AddrBits / 8 // unused 102 val DataBits = XLEN 103 val DataBytes = DataBits / 8 104 val HasFPU = core.HasFPU 105 val FetchWidth = core.FectchWidth 106 val PredictWidth = FetchWidth * 2 107 val EnableBPU = core.EnableBPU 108 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 109 val EnableRAS = core.EnableRAS 110 val EnableLB = core.EnableLB 111 val HistoryLength = core.HistoryLength 112 val BtbSize = core.BtbSize 113 // val BtbWays = 4 114 val BtbBanks = PredictWidth 115 // val BtbSets = BtbSize / BtbWays 116 val JbtacSize = core.JbtacSize 117 val JbtacBanks = core.JbtacBanks 118 val RasSize = core.RasSize 119 val CacheLineSize = core.CacheLineSize 120 val CacheLineHalfWord = CacheLineSize / 16 121 val ExtHistoryLength = HistoryLength * 2 122 val UBtbWays = core.UBtbWays 123 val BtbWays = core.BtbWays 124 val IBufSize = core.IBufSize 125 val DecodeWidth = core.DecodeWidth 126 val RenameWidth = core.RenameWidth 127 val CommitWidth = core.CommitWidth 128 val BrqSize = core.BrqSize 129 val IssQueSize = core.IssQueSize 130 val BrTagWidth = log2Up(BrqSize) 131 val NRPhyRegs = core.NRPhyRegs 132 val PhyRegIdxWidth = log2Up(NRPhyRegs) 133 val LsroqSize = core.LsroqSize // 64 134 val RoqSize = core.RoqSize 135 val InnerRoqIdxWidth = log2Up(RoqSize) 136 val RoqIdxWidth = InnerRoqIdxWidth + 1 137 val InnerLsroqIdxWidth = log2Up(LsroqSize) 138 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 139 val IntDqDeqWidth = core.IntDqDeqWidth 140 val FpDqDeqWidth = core.FpDqDeqWidth 141 val LsDqDeqWidth = core.LsDqDeqWidth 142 val ReplayWidth = core.ReplayWidth 143 val dpParams = core.dpParams 144 val exuParameters = core.exuParameters 145 val NRIntReadPorts = core.NRIntReadPorts 146 val NRIntWritePorts = core.NRIntWritePorts 147 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 148 val NRFpReadPorts = core.NRFpReadPorts 149 val NRFpWritePorts = core.NRFpWritePorts 150 val LoadPipelineWidth = core.LoadPipelineWidth 151 val StorePipelineWidth = core.StorePipelineWidth 152 val StoreBufferSize = core.StoreBufferSize 153 val RefillSize = core.RefillSize 154} 155 156trait HasXSLog { this: Module => 157 implicit val moduleName: String = this.name 158} 159 160abstract class XSModule extends Module 161 with HasXSParameter 162 with HasExceptionNO 163 with HasXSLog 164 165//remove this trait after impl module logic 166trait NeedImpl { this: Module => 167 override protected def IO[T <: Data](iodef: T): T = { 168 val io = chisel3.experimental.IO(iodef) 169 io <> DontCare 170 io 171 } 172} 173 174abstract class XSBundle extends Bundle 175 with HasXSParameter 176 177case class EnviromentParameters 178( 179 FPGAPlatform: Boolean = true, 180 EnableDebug: Boolean = false 181) 182 183object AddressSpace extends HasXSParameter { 184 // (start, size) 185 // address out of MMIO will be considered as DRAM 186 def mmio = List( 187 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 188 (0x40000000L, 0x40000000L) // external devices 189 ) 190 191 def isMMIO(addr: UInt): Bool = mmio.map(range => { 192 require(isPow2(range._2)) 193 val bits = log2Up(range._2) 194 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 195 }).reduce(_ || _) 196} 197 198 199class XSCore extends XSModule { 200 val io = IO(new Bundle { 201 val imem = new SimpleBusC 202 val dmem = new SimpleBusC 203 val mmio = new SimpleBusUC 204 val frontend = Flipped(new SimpleBusUC()) 205 }) 206 207 io.imem <> DontCare 208 209 val DcacheUserBundleWidth = (new DcacheUserBundle).getWidth 210 211 val dmemXbar = Module(new SimpleBusCrossbarNto1(n = 2, userBits = DcacheUserBundleWidth)) 212 213 val front = Module(new Frontend) 214 val backend = Module(new Backend) 215 val mem = Module(new Memend) 216 217 front.io.backend <> backend.io.frontend 218 mem.io.backend <> backend.io.mem 219 220 backend.io.memMMU.imem <> DontCare 221 222 val dtlb = TLB( 223 in = mem.io.dmem, 224 mem = dmemXbar.io.in(1), 225 flush = false.B, 226 csrMMU = backend.io.memMMU.dmem 227 )(TLBConfig(name = "dtlb", totalEntry = 64, userBits = DcacheUserBundleWidth)) 228 dmemXbar.io.in(0) <> dtlb.io.out 229 // dmemXbar.io.in(1) <> io.frontend 230 231 io.frontend <> DontCare 232 233 io.dmem <> Cache( 234 in = dmemXbar.io.out, 235 mmio = Seq(io.mmio), 236 flush = "b00".U, 237 empty = dtlb.io.cacheEmpty, 238 enable = HasDcache 239 )(CacheConfig(name = "dcache", userBits = DcacheUserBundleWidth)) 240 241} 242