1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.backend._ 6import xiangshan.backend.fu.HasExceptionNO 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.frontend._ 9import xiangshan.mem._ 10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheWrapper, L1plusCacheParameters, PTWWrapper, PTWRepeater, PTWFilter} 11import xiangshan.cache.prefetch._ 12import chipsalliance.rocketchip.config 13import chipsalliance.rocketchip.config.Parameters 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tile.HasFPUParameters 16import system.{HasSoCParameter, L1CacheErrorInfo} 17import utils._ 18 19object hartIdCore extends (() => Int) { 20 var x = 0 21 22 def apply(): Int = { 23 x = x + 1 24 x - 1 25 } 26} 27 28abstract class XSModule(implicit val p: Parameters) extends MultiIOModule 29 with HasXSParameter 30 with HasExceptionNO 31 with HasFPUParameters { 32 def io: Record 33} 34 35//remove this trait after impl module logic 36trait NeedImpl { 37 this: RawModule => 38 override protected def IO[T <: Data](iodef: T): T = { 39 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 40 val io = chisel3.experimental.IO(iodef) 41 io <> DontCare 42 io 43 } 44} 45 46abstract class XSBundle(implicit val p: Parameters) extends Bundle 47 with HasXSParameter 48 49case class EnviromentParameters 50( 51 FPGAPlatform: Boolean = true, 52 EnableDebug: Boolean = false, 53 EnablePerfDebug: Boolean = true, 54 DualCore: Boolean = false 55) 56 57class XSCore()(implicit p: config.Parameters) extends LazyModule 58 with HasXSParameter 59 with HasExeBlockHelper { 60 // outer facing nodes 61 val frontend = LazyModule(new Frontend()) 62 val l1pluscache = LazyModule(new L1plusCacheWrapper()) 63 val ptw = LazyModule(new PTWWrapper()) 64 val memBlock = LazyModule(new MemBlock( 65 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 66 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 67 fastWakeUpOut = Seq(), 68 slowWakeUpOut = loadExuConfigs, 69 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 70 )) 71 72 lazy val module = new XSCoreImp(this) 73} 74 75class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 76 with HasXSParameter 77 with HasSoCParameter 78 with HasExeBlockHelper { 79 val io = IO(new Bundle { 80 val hartId = Input(UInt(64.W)) 81 val externalInterrupt = new ExternalInterruptIO 82 val l2_pf_enable = Output(Bool()) 83 val l1plus_error, icache_error, dcache_error = Output(new L1CacheErrorInfo) 84 }) 85 86 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 87 AddressSpace.checkMemmap() 88 AddressSpace.printMemmap() 89 90 // to fast wake up fp, mem rs 91 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 92 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 93 94 val ctrlBlock = Module(new CtrlBlock) 95 val integerBlock = Module(new IntegerBlock( 96 fastWakeUpIn = Seq(), 97 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 98 memFastWakeUpIn = loadExuConfigs, 99 fastWakeUpOut = intBlockFastWakeUp, 100 slowWakeUpOut = intBlockSlowWakeUp 101 )) 102 val floatBlock = Module(new FloatBlock( 103 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 104 memSlowWakeUpIn = loadExuConfigs, 105 fastWakeUpOut = Seq(), 106 slowWakeUpOut = fpExuConfigs 107 )) 108 109 val frontend = outer.frontend.module 110 val memBlock = outer.memBlock.module 111 val l1pluscache = outer.l1pluscache.module 112 val ptw = outer.ptw.module 113 114 io.l1plus_error <> l1pluscache.io.error 115 io.icache_error <> frontend.io.error 116 io.dcache_error <> memBlock.io.error 117 118 frontend.io.backend <> ctrlBlock.io.frontend 119 frontend.io.sfence <> integerBlock.io.fenceio.sfence 120 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 121 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 122 123 frontend.io.icacheMemAcq <> l1pluscache.io.req 124 l1pluscache.io.resp <> frontend.io.icacheMemGrant 125 l1pluscache.io.flush := frontend.io.l1plusFlush 126 frontend.io.fencei := integerBlock.io.fenceio.fencei 127 128 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 129 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 130 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 131 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 132 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 133 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 134 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 135 136 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 137 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 138 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 139 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 140 141 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 142 val fpBlockWakeUpInt = fpExuConfigs 143 .zip(floatBlock.io.wakeUpOut.slow) 144 .filter(_._1.writeIntRf) 145 .map(_._2) 146 147 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 148 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 149 .zip(integerBlock.io.wakeUpOut.slow) 150 .filter(_._1.writeFpRf) 151 .map(_._2) 152 153 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 154 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 155 integerBlock.io.memFastWakeUp <> memBlock.io.ldFastWakeUpInt 156 157 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 158 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 159 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 160 161 val wakeUpMem = Seq( 162 integerBlock.io.wakeUpOut, 163 floatBlock.io.wakeUpOut, 164 ) 165 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 166 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 167 // Note: 'WireInit' is used to block 'ready's from memBlock, 168 // we don't need 'ready's from memBlock 169 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 170 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 171 memBlock.io.intWbOut := integerBlock.io.intWbOut 172 memBlock.io.fpWbOut := floatBlock.io.fpWbOut 173 174 integerBlock.io.csrio.hartId <> io.hartId 175 integerBlock.io.csrio.perf <> DontCare 176 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 177 integerBlock.io.csrio.perf.bpuInfo <> ctrlBlock.io.perfInfo.bpuInfo 178 integerBlock.io.csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 179 integerBlock.io.csrio.perf.memInfo <> memBlock.io.memInfo 180 integerBlock.io.csrio.perf.frontendInfo <> frontend.io.frontendInfo 181 182 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 183 integerBlock.io.csrio.fpu.isIllegal := false.B 184 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 185 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 186 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 187 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 188 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 189 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 190 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 191 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 192 193 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 194 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 195 196 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 197 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 198 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 199 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 200 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 201 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 202 203 val itlbRepeater = Module(new PTWRepeater()) 204 val dtlbRepeater = Module(new PTWFilter(LoadPipelineWidth + StorePipelineWidth, PtwMissQueueSize)) 205 itlbRepeater.io.tlb <> frontend.io.ptw 206 dtlbRepeater.io.tlb <> memBlock.io.ptw 207 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 208 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 209 ptw.io.tlb(0) <> itlbRepeater.io.ptw 210 ptw.io.tlb(1) <> dtlbRepeater.io.ptw 211 ptw.io.sfence <> integerBlock.io.fenceio.sfence 212 ptw.io.csr <> integerBlock.io.csrio.tlb 213 214 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 215 assert(l2PrefetcherParameters._type == "bop") 216 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 217 218 val l1plus_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform)) 219 l1pluscache.reset := l1plus_reset_gen.io.out 220 221 val ptw_reset_gen = Module(new ResetGen(2, !debugOpts.FPGAPlatform)) 222 ptw.reset := ptw_reset_gen.io.out 223 itlbRepeater.reset := ptw_reset_gen.io.out 224 dtlbRepeater.reset := ptw_reset_gen.io.out 225 226 val memBlock_reset_gen = Module(new ResetGen(3, !debugOpts.FPGAPlatform)) 227 memBlock.reset := memBlock_reset_gen.io.out 228 229 val intBlock_reset_gen = Module(new ResetGen(4, !debugOpts.FPGAPlatform)) 230 integerBlock.reset := intBlock_reset_gen.io.out 231 232 val fpBlock_reset_gen = Module(new ResetGen(5, !debugOpts.FPGAPlatform)) 233 floatBlock.reset := fpBlock_reset_gen.io.out 234 235 val ctrlBlock_reset_gen = Module(new ResetGen(6, !debugOpts.FPGAPlatform)) 236 ctrlBlock.reset := ctrlBlock_reset_gen.io.out 237 238 val frontend_reset_gen = Module(new ResetGen(7, !debugOpts.FPGAPlatform)) 239 frontend.reset := frontend_reset_gen.io.out 240} 241