1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.exu.ExuConfig 9import xiangshan.frontend.Frontend 10 11trait HasXSParameter { 12 val XLEN = 64 13 val HasMExtension = true 14 val HasCExtension = true 15 val HasDiv = true 16 val HasIcache = true 17 val HasDcache = true 18 val EnableStoreQueue = false 19 val AddrBits = 64 // AddrBits is used in some cases 20 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 21 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 22 val AddrBytes = AddrBits / 8 // unused 23 val DataBits = XLEN 24 val DataBytes = DataBits / 8 25 val HasFPU = true 26 val FetchWidth = 8 27 val IBufSize = 64 28 val DecodeWidth = 6 29 val CommitWidth = 6 30 val BrqSize = 16 31 val BrTagWidth = log2Up(BrqSize) 32 val NRPhyRegs = 96 33 val PhyRegIdxWidth = log2Up(NRPhyRegs) 34 val NRReadPorts = 14 35 val NRWritePorts = 8 36 val RoqSize = 128 37 val RoqIdxWidth = log2Up(RoqSize) 38 val IntDqDeqWidth = 4 39 val FpDqDeqWidth = 4 40 val LsDqDeqWidth = 4 41 val exuConfig = ExuConfig( 42 AluCnt = 4, 43 BruCnt = 1, 44 MulCnt = 1, 45 MduCnt = 1, 46 FmacCnt = 4, 47 FmiscCnt = 1, 48 FmiscDivSqrtCnt = 1, 49 LsuCnt = 1 50 ) 51} 52 53abstract class XSModule extends Module 54 with HasXSParameter 55 with HasExceptionNO 56 57//remove this trait after impl module logic 58trait NeedImpl { this: Module => 59 override protected def IO[T <: Data](iodef: T): T = { 60 val io = chisel3.experimental.IO(iodef) 61 io <> DontCare 62 io 63 } 64} 65 66abstract class XSBundle extends Bundle 67 with HasXSParameter 68 69case class XSConfig 70( 71 FPGAPlatform: Boolean = true, 72 EnableDebug: Boolean = false 73) 74 75class XSCore(implicit val p: XSConfig) extends XSModule { 76 val io = IO(new Bundle { 77 val imem = new SimpleBusC 78 val dmem = new SimpleBusC 79 val mmio = new SimpleBusUC 80 val frontend = Flipped(new SimpleBusUC()) 81 }) 82 83 io.imem <> DontCare 84 85 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 86 87 val front = Module(new Frontend) 88 val backend = Module(new Backend) 89 90 front.io.backend <> backend.io.frontend 91 92 backend.io.memMMU.imem <> DontCare 93 94 val dtlb = TLB( 95 in = backend.io.dmem, 96 mem = dmemXbar.io.in(1), 97 flush = false.B, 98 csrMMU = backend.io.memMMU.dmem 99 )(TLBConfig(name = "dtlb", totalEntry = 64)) 100 dmemXbar.io.in(0) <> dtlb.io.out 101 dmemXbar.io.in(2) <> io.frontend 102 103 io.dmem <> Cache( 104 in = dmemXbar.io.out, 105 mmio = Seq(io.mmio), 106 flush = "b00".U, 107 empty = dtlb.io.cacheEmpty, 108 enable = HasDcache 109 )(CacheConfig(name = "dcache")) 110} 111