1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache,InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache, MemoryOpConstants, MissReq} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 21import freechips.rocketchip.tile.HasFPUParameters 22import sifive.blocks.inclusivecache.PrefetcherIO 23import utils._ 24 25case class XSCoreParameters 26( 27 XLEN: Int = 64, 28 HasMExtension: Boolean = true, 29 HasCExtension: Boolean = true, 30 HasDiv: Boolean = true, 31 HasICache: Boolean = true, 32 HasDCache: Boolean = true, 33 EnableStoreQueue: Boolean = true, 34 AddrBits: Int = 64, 35 VAddrBits: Int = 39, 36 PAddrBits: Int = 40, 37 HasFPU: Boolean = true, 38 FectchWidth: Int = 8, 39 EnableBPU: Boolean = true, 40 EnableBPD: Boolean = true, 41 EnableRAS: Boolean = true, 42 EnableLB: Boolean = false, 43 EnableLoop: Boolean = false, 44 EnableSC: Boolean = false, 45 HistoryLength: Int = 64, 46 BtbSize: Int = 2048, 47 JbtacSize: Int = 1024, 48 JbtacBanks: Int = 8, 49 RasSize: Int = 16, 50 CacheLineSize: Int = 512, 51 UBtbWays: Int = 16, 52 BtbWays: Int = 2, 53 54 EnableL1plusPrefetcher: Boolean = true, 55 IBufSize: Int = 32, 56 DecodeWidth: Int = 6, 57 RenameWidth: Int = 6, 58 CommitWidth: Int = 6, 59 BrqSize: Int = 32, 60 FtqSize: Int = 48, 61 IssQueSize: Int = 12, 62 NRPhyRegs: Int = 160, 63 NRIntReadPorts: Int = 14, 64 NRIntWritePorts: Int = 8, 65 NRFpReadPorts: Int = 14, 66 NRFpWritePorts: Int = 8, 67 LoadQueueSize: Int = 64, 68 StoreQueueSize: Int = 48, 69 RoqSize: Int = 192, 70 dpParams: DispatchParameters = DispatchParameters( 71 IntDqSize = 32, 72 FpDqSize = 32, 73 LsDqSize = 32, 74 IntDqDeqWidth = 4, 75 FpDqDeqWidth = 4, 76 LsDqDeqWidth = 4 77 ), 78 exuParameters: ExuParameters = ExuParameters( 79 JmpCnt = 1, 80 AluCnt = 4, 81 MulCnt = 0, 82 MduCnt = 2, 83 FmacCnt = 4, 84 FmiscCnt = 2, 85 FmiscDivSqrtCnt = 0, 86 LduCnt = 2, 87 StuCnt = 2 88 ), 89 LoadPipelineWidth: Int = 2, 90 StorePipelineWidth: Int = 2, 91 StoreBufferSize: Int = 16, 92 RefillSize: Int = 512, 93 TlbEntrySize: Int = 32, 94 TlbSPEntrySize: Int = 4, 95 TlbL2EntrySize: Int = 256, // or 512 96 TlbL2SPEntrySize: Int = 16, 97 PtwL1EntrySize: Int = 16, 98 PtwL2EntrySize: Int = 256, 99 NumPerfCounters: Int = 16, 100 NrExtIntr: Int = 1 101) 102 103trait HasXSParameter { 104 105 val core = Parameters.get.coreParameters 106 val env = Parameters.get.envParameters 107 108 val XLEN = 64 109 val minFLen = 32 110 val fLen = 64 111 def xLen = 64 112 val HasMExtension = core.HasMExtension 113 val HasCExtension = core.HasCExtension 114 val HasDiv = core.HasDiv 115 val HasIcache = core.HasICache 116 val HasDcache = core.HasDCache 117 val EnableStoreQueue = core.EnableStoreQueue 118 val AddrBits = core.AddrBits // AddrBits is used in some cases 119 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 120 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 121 val AddrBytes = AddrBits / 8 // unused 122 val DataBits = XLEN 123 val DataBytes = DataBits / 8 124 val HasFPU = core.HasFPU 125 val FetchWidth = core.FectchWidth 126 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 127 val EnableBPU = core.EnableBPU 128 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 129 val EnableRAS = core.EnableRAS 130 val EnableLB = core.EnableLB 131 val EnableLoop = core.EnableLoop 132 val EnableSC = core.EnableSC 133 val HistoryLength = core.HistoryLength 134 val BtbSize = core.BtbSize 135 // val BtbWays = 4 136 val BtbBanks = PredictWidth 137 // val BtbSets = BtbSize / BtbWays 138 val JbtacSize = core.JbtacSize 139 val JbtacBanks = core.JbtacBanks 140 val RasSize = core.RasSize 141 val CacheLineSize = core.CacheLineSize 142 val CacheLineHalfWord = CacheLineSize / 16 143 val ExtHistoryLength = HistoryLength + 64 144 val UBtbWays = core.UBtbWays 145 val BtbWays = core.BtbWays 146 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 147 val IBufSize = core.IBufSize 148 val DecodeWidth = core.DecodeWidth 149 val RenameWidth = core.RenameWidth 150 val CommitWidth = core.CommitWidth 151 val BrqSize = core.BrqSize 152 val FtqSize = core.FtqSize 153 val IssQueSize = core.IssQueSize 154 val BrTagWidth = log2Up(BrqSize) 155 val NRPhyRegs = core.NRPhyRegs 156 val PhyRegIdxWidth = log2Up(NRPhyRegs) 157 val RoqSize = core.RoqSize 158 val LoadQueueSize = core.LoadQueueSize 159 val StoreQueueSize = core.StoreQueueSize 160 val dpParams = core.dpParams 161 val exuParameters = core.exuParameters 162 val NRIntReadPorts = core.NRIntReadPorts 163 val NRIntWritePorts = core.NRIntWritePorts 164 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 165 val NRFpReadPorts = core.NRFpReadPorts 166 val NRFpWritePorts = core.NRFpWritePorts 167 val LoadPipelineWidth = core.LoadPipelineWidth 168 val StorePipelineWidth = core.StorePipelineWidth 169 val StoreBufferSize = core.StoreBufferSize 170 val RefillSize = core.RefillSize 171 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 172 val TlbEntrySize = core.TlbEntrySize 173 val TlbSPEntrySize = core.TlbSPEntrySize 174 val TlbL2EntrySize = core.TlbL2EntrySize 175 val TlbL2SPEntrySize = core.TlbL2SPEntrySize 176 val PtwL1EntrySize = core.PtwL1EntrySize 177 val PtwL2EntrySize = core.PtwL2EntrySize 178 val NumPerfCounters = core.NumPerfCounters 179 val NrExtIntr = core.NrExtIntr 180 181 val instBytes = if (HasCExtension) 2 else 4 182 val instOffsetBits = log2Ceil(instBytes) 183 184 val icacheParameters = ICacheParameters( 185 tagECC = Some("parity"), 186 dataECC = Some("parity"), 187 nMissEntries = 2 188 ) 189 190 val l1plusCacheParameters = L1plusCacheParameters( 191 tagECC = Some("secded"), 192 dataECC = Some("secded"), 193 nMissEntries = 8 194 ) 195 196 val dcacheParameters = DCacheParameters( 197 tagECC = Some("secded"), 198 dataECC = Some("secded"), 199 nMissEntries = 16, 200 nLoadMissEntries = 8, 201 nStoreMissEntries = 8 202 ) 203 204 val LRSCCycles = 100 205 206 207 // cache hierarchy configurations 208 val l1BusDataWidth = 256 209 210 // L2 configurations 211 val L1BusWidth = 256 212 val L2Size = 512 * 1024 // 512KB 213 val L2BlockSize = 64 214 val L2NWays = 8 215 val L2NSets = L2Size / L2BlockSize / L2NWays 216 217 // L3 configurations 218 val L2BusWidth = 256 219 val L3Size = 4 * 1024 * 1024 // 4MB 220 val L3BlockSize = 64 221 val L3NBanks = 4 222 val L3NWays = 8 223 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 224 225 // on chip network configurations 226 val L3BusWidth = 256 227 228 // icache prefetcher 229 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 230 enable = true, 231 _type = "stream", 232 streamParams = StreamPrefetchParameters( 233 streamCnt = 2, 234 streamSize = 4, 235 ageWidth = 4, 236 blockBytes = l1plusCacheParameters.blockBytes, 237 reallocStreamOnMissInstantly = true, 238 cacheName = "icache" 239 ) 240 ) 241 242 // dcache prefetcher 243 val l2PrefetcherParameters = L2PrefetcherParameters( 244 enable = true, 245 _type = "bop",// "stream" or "bop" 246 streamParams = StreamPrefetchParameters( 247 streamCnt = 4, 248 streamSize = 4, 249 ageWidth = 4, 250 blockBytes = L2BlockSize, 251 reallocStreamOnMissInstantly = true, 252 cacheName = "dcache" 253 ), 254 bopParams = BOPParameters( 255 rrTableEntries = 256, 256 rrTagBits = 12, 257 scoreBits = 5, 258 roundMax = 50, 259 badScore = 1, 260 blockBytes = L2BlockSize, 261 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 262 ), 263 ) 264} 265 266trait HasXSLog { this: RawModule => 267 implicit val moduleName: String = this.name 268} 269 270abstract class XSModule extends MultiIOModule 271 with HasXSParameter 272 with HasExceptionNO 273 with HasXSLog 274 with HasFPUParameters 275{ 276 def io: Record 277} 278 279//remove this trait after impl module logic 280trait NeedImpl { this: RawModule => 281 override protected def IO[T <: Data](iodef: T): T = { 282 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 283 val io = chisel3.experimental.IO(iodef) 284 io <> DontCare 285 io 286 } 287} 288 289abstract class XSBundle extends Bundle 290 with HasXSParameter 291 292case class EnviromentParameters 293( 294 FPGAPlatform: Boolean = true, 295 EnableDebug: Boolean = false, 296 EnablePerfDebug: Boolean = false 297) 298 299// object AddressSpace extends HasXSParameter { 300// // (start, size) 301// // address out of MMIO will be considered as DRAM 302// def mmio = List( 303// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 304// (0x40000000L, 0x40000000L) // external devices 305// ) 306 307// def isMMIO(addr: UInt): Bool = mmio.map(range => { 308// require(isPow2(range._2)) 309// val bits = log2Up(range._2) 310// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 311// }).reduce(_ || _) 312// } 313 314 315 316class XSCore()(implicit p: config.Parameters) extends LazyModule 317 with HasXSParameter 318 with HasExeBlockHelper 319{ 320 321 // to fast wake up fp, mem rs 322 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 323 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 324 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 325 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 326 327 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 328 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 329 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 330 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 331 332 // outer facing nodes 333 val frontend = LazyModule(new Frontend()) 334 val l1pluscache = LazyModule(new L1plusCache()) 335 val ptw = LazyModule(new PTW()) 336 val l2Prefetcher = LazyModule(new L2Prefetcher()) 337 val memBlock = LazyModule(new MemBlock( 338 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 339 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 340 fastFpOut = Seq(), 341 slowFpOut = loadExuConfigs, 342 fastIntOut = Seq(), 343 slowIntOut = loadExuConfigs 344 )) 345 346 lazy val module = new XSCoreImp(this) 347} 348 349class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 350 with HasXSParameter 351 with HasExeBlockHelper 352{ 353 val io = IO(new Bundle { 354 val externalInterrupt = new ExternalInterruptIO 355 val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits)) 356 }) 357 358 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 359 AddressSpace.printMemmap() 360 361 // to fast wake up fp, mem rs 362 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 363 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 364 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 365 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 366 367 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 368 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 369 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 370 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 371 372 val ctrlBlock = Module(new CtrlBlock) 373 val integerBlock = Module(new IntegerBlock( 374 fastWakeUpIn = fpBlockFastWakeUpInt, 375 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 376 fastFpOut = intBlockFastWakeUpFp, 377 slowFpOut = intBlockSlowWakeUpFp, 378 fastIntOut = intBlockFastWakeUpInt, 379 slowIntOut = intBlockSlowWakeUpInt 380 )) 381 val floatBlock = Module(new FloatBlock( 382 fastWakeUpIn = intBlockFastWakeUpFp, 383 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 384 fastFpOut = fpBlockFastWakeUpFp, 385 slowFpOut = fpBlockSlowWakeUpFp, 386 fastIntOut = fpBlockFastWakeUpInt, 387 slowIntOut = fpBlockSlowWakeUpInt 388 )) 389 390 val frontend = outer.frontend.module 391 val memBlock = outer.memBlock.module 392 val l1pluscache = outer.l1pluscache.module 393 val ptw = outer.ptw.module 394 val l2Prefetcher = outer.l2Prefetcher.module 395 396 frontend.io.backend <> ctrlBlock.io.frontend 397 frontend.io.sfence <> integerBlock.io.fenceio.sfence 398 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 399 400 frontend.io.icacheMemAcq <> l1pluscache.io.req 401 l1pluscache.io.resp <> frontend.io.icacheMemGrant 402 l1pluscache.io.flush := frontend.io.l1plusFlush 403 frontend.io.fencei := integerBlock.io.fenceio.fencei 404 405 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 406 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 407 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 408 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 409 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 410 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 411 412 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 413 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 414 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 415 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 416 417 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 418 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 419 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 420 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 421 422 423 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 424 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 425 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 426 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 427 428 val wakeUpMem = Seq( 429 integerBlock.io.wakeUpIntOut, 430 integerBlock.io.wakeUpFpOut, 431 floatBlock.io.wakeUpIntOut, 432 floatBlock.io.wakeUpFpOut 433 ) 434 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 435 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 436 val raw = WireInit(f) 437 raw 438 })) 439 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 440 val raw = WireInit(s) 441 raw 442 })) 443 444 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 445 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 446 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 447 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 448 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 449 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 450 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 451 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 452 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 453 integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo 454 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 455 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 456 457 floatBlock.io.frm <> integerBlock.io.csrio.frm 458 459 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 460 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 461 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 462 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 463 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 464 465 ptw.io.tlb(0) <> memBlock.io.ptw 466 ptw.io.tlb(1) <> frontend.io.ptw 467 ptw.io.sfence <> integerBlock.io.fenceio.sfence 468 ptw.io.csr <> integerBlock.io.csrio.tlb 469 470 val l2PrefetcherIn = Wire(Decoupled(new MissReq)) 471 if (l2PrefetcherParameters.enable && l2PrefetcherParameters._type == "bop") { 472 l2PrefetcherIn.valid := io.l2ToPrefetcher.acquire.valid 473 l2PrefetcherIn.bits := DontCare 474 l2PrefetcherIn.bits.addr := io.l2ToPrefetcher.acquire.bits.address 475 l2PrefetcherIn.bits.cmd := Mux(io.l2ToPrefetcher.acquire.bits.write, MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD) 476 } else { 477 l2PrefetcherIn <> memBlock.io.toDCachePrefetch 478 } 479 l2Prefetcher.io.in <> l2PrefetcherIn 480 481 if (!env.FPGAPlatform) { 482 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 483 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 484 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 485 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 486 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 487 } 488 489} 490