xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 55854ee115e7e4d017b25a54dd8edbbde18dbf95) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Config
9import xiangshan.backend.exu.ExuConfig
10import xiangshan.frontend.Frontend
11import xiangshan.utils._
12
13trait HasXSParameter {
14  val XLEN = 64
15  val HasMExtension = true
16  val HasCExtension = true
17  val HasDiv = true
18  val HasIcache = true
19  val HasDcache = true
20  val EnableStoreQueue = false
21  val AddrBits = 64 // AddrBits is used in some cases
22  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
23  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
24  val AddrBytes = AddrBits / 8 // unused
25  val DataBits = XLEN
26  val DataBytes = DataBits / 8
27  val HasFPU = true
28  val FetchWidth = 8
29  val IBufSize = 64
30  val DecodeWidth = 8
31  val DecBufSize = 8
32  val RenameWidth = 6
33  val CommitWidth = 6
34  val BrqSize = 16
35  val BrTagWidth = log2Up(BrqSize)
36  val NRPhyRegs = 128
37  val PhyRegIdxWidth = log2Up(NRPhyRegs)
38  val NRReadPorts = 14
39  val NRWritePorts = 8
40  val RoqSize = 32
41  val RoqIdxWidth = log2Up(RoqSize)
42  val ExtendedRoqIdxWidth = RoqIdxWidth + 1
43  val IntDqDeqWidth = 4
44  val FpDqDeqWidth = 4
45  val LsDqDeqWidth = 4
46  val dp1Config = DP1Config(
47    IntDqSize = 16,
48    FpDqSize = 16,
49    LsDqSize = 16
50  )
51  val exuConfig = ExuConfig(
52    AluCnt = 4,
53    BruCnt = 1,
54    MulCnt = 1,
55    MduCnt = 1,
56    FmacCnt = 4,
57    FmiscCnt = 1,
58    FmiscDivSqrtCnt = 1,
59    LduCnt = 1,
60    StuCnt = 1
61  )
62}
63
64trait HasXSLog { this: Module =>
65  implicit val moduleName: String = this.name
66}
67
68abstract class XSModule extends Module
69  with HasXSParameter
70  with HasExceptionNO
71  with HasXSLog
72
73//remove this trait after impl module logic
74trait NeedImpl { this: Module =>
75  override protected def IO[T <: Data](iodef: T): T = {
76    val io = chisel3.experimental.IO(iodef)
77    io <> DontCare
78    io
79  }
80}
81
82abstract class XSBundle extends Bundle
83  with HasXSParameter
84
85case class XSConfig
86(
87  FPGAPlatform: Boolean = true,
88  EnableDebug: Boolean = false
89)
90
91class XSCore(implicit val p: XSConfig) extends XSModule {
92  val io = IO(new Bundle {
93    val imem = new SimpleBusC
94    val dmem = new SimpleBusC
95    val mmio = new SimpleBusUC
96    val frontend = Flipped(new SimpleBusUC())
97  })
98
99  io.imem <> DontCare
100
101  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
102
103  val front = Module(new Frontend)
104  val backend = Module(new Backend)
105
106  front.io.backend <> backend.io.frontend
107
108  backend.io.memMMU.imem <> DontCare
109
110  val dtlb = TLB(
111    in = backend.io.dmem,
112    mem = dmemXbar.io.in(1),
113    flush = false.B,
114    csrMMU = backend.io.memMMU.dmem
115  )(TLBConfig(name = "dtlb", totalEntry = 64))
116  dmemXbar.io.in(0) <> dtlb.io.out
117  dmemXbar.io.in(2) <> io.frontend
118
119  io.dmem <> Cache(
120    in = dmemXbar.io.out,
121    mmio = Seq(io.mmio),
122    flush = "b00".U,
123    empty = dtlb.io.cacheEmpty,
124    enable = HasDcache
125  )(CacheConfig(name = "dcache"))
126}
127