1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DispatchParameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import utils._ 13 14trait HasXSParameter { 15 val XLEN = 64 16 val HasMExtension = true 17 val HasCExtension = true 18 val HasDiv = true 19 val HasIcache = true 20 val HasDcache = true 21 val EnableStoreQueue = false 22 val AddrBits = 64 // AddrBits is used in some cases 23 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 24 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 25 val AddrBytes = AddrBits / 8 // unused 26 val DataBits = XLEN 27 val DataBytes = DataBits / 8 28 val CacheLineSize = 512 29 val SbufferSize = 16 30 val HasFPU = true 31 val FetchWidth = 8 32 val PredictWidth = FetchWidth * 2 33 val EnableBPU = true 34 val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3 35 val EnableRAS = false 36 val HistoryLength = 64 37 val BtbSize = 256 38 // val BtbWays = 4 39 val BtbBanks = PredictWidth 40 // val BtbSets = BtbSize / BtbWays 41 val JbtacSize = 1024 42 val JbtacBanks = 8 43 val RasSize = 16 44 val IBufSize = 64 45 val DecodeWidth = 6 46 val RenameWidth = 6 47 val CommitWidth = 6 48 val BrqSize = 16 49 val IssQueSize = 8 50 val BrTagWidth = log2Up(BrqSize) 51 val NRPhyRegs = 128 52 val PhyRegIdxWidth = log2Up(NRPhyRegs) 53 val exuParameters = ExuParameters( 54 JmpCnt = 1, 55 AluCnt = 4, 56 MulCnt = 0, 57 MduCnt = 2, 58 FmacCnt = 0, 59 FmiscCnt = 0, 60 FmiscDivSqrtCnt = 0, 61 LduCnt = 2, 62 StuCnt = 2 63 ) 64 val NRIntReadPorts = 8 65 val NRIntWritePorts = 8 66 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 67 val NRFpReadPorts = 14 68 val NRFpWritePorts = 8 69 val MoqSize = 16 // 64 70 val RoqSize = 32 71 val InnerRoqIdxWidth = log2Up(RoqSize) 72 val RoqIdxWidth = InnerRoqIdxWidth + 1 73 val InnerMoqIdxWidth = log2Up(MoqSize) 74 val MoqIdxWidth = InnerMoqIdxWidth + 1 75 val dpParams = DispatchParameters( 76 DqEnqWidth = 4, 77 IntDqSize = 64, 78 FpDqSize = 64, 79 LsDqSize = 64, 80 IntDqDeqWidth = 4, 81 FpDqDeqWidth = 4, 82 LsDqDeqWidth = 4 83 ) 84} 85 86trait HasXSLog { this: Module => 87 implicit val moduleName: String = this.name 88} 89 90abstract class XSModule extends Module 91 with HasXSParameter 92 with HasExceptionNO 93 with HasXSLog 94 95//remove this trait after impl module logic 96trait NeedImpl { this: Module => 97 override protected def IO[T <: Data](iodef: T): T = { 98 val io = chisel3.experimental.IO(iodef) 99 io <> DontCare 100 io 101 } 102} 103 104abstract class XSBundle extends Bundle 105 with HasXSParameter 106 107case class XSConfig 108( 109 FPGAPlatform: Boolean = true, 110 EnableDebug: Boolean = true 111) 112 113object AddressSpace extends HasXSParameter { 114 // (start, size) 115 // address out of MMIO will be considered as DRAM 116 def mmio = List( 117 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 118 (0x40000000L, 0x40000000L) // external devices 119 ) 120 121 def isMMIO(addr: UInt): Bool = mmio.map(range => { 122 require(isPow2(range._2)) 123 val bits = log2Up(range._2) 124 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 125 }).reduce(_ || _) 126} 127 128 129class XSCore(implicit p: XSConfig) extends XSModule with HasMEMConst { 130 val io = IO(new Bundle { 131 val imem = new SimpleBusC 132 val dmem = new SimpleBusC 133 val mmio = new SimpleBusUC 134 val frontend = Flipped(new SimpleBusUC()) 135 }) 136 137 io.imem <> DontCare 138 139 val dmemXbar = Module(new SimpleBusCrossbarNto1(n = 2, userBits = DcacheUserBundleWidth)) 140 141 val front = Module(new Frontend) 142 val backend = Module(new Backend) 143 val mem = Module(new Memend) 144 145 front.io.backend <> backend.io.frontend 146 mem.io.backend <> backend.io.mem 147 148 backend.io.memMMU.imem <> DontCare 149 150 val dtlb = TLB( 151 in = mem.io.dmem, 152 mem = dmemXbar.io.in(1), 153 flush = false.B, 154 csrMMU = backend.io.memMMU.dmem 155 )(TLBConfig(name = "dtlb", totalEntry = 64, userBits = DcacheUserBundleWidth)) 156 dmemXbar.io.in(0) <> dtlb.io.out 157 // dmemXbar.io.in(1) <> io.frontend 158 159 io.frontend <> DontCare 160 161 io.dmem <> Cache( 162 in = dmemXbar.io.out, 163 mmio = Seq(io.mmio), 164 flush = "b00".U, 165 empty = dtlb.io.cacheEmpty, 166 enable = HasDcache 167 )(CacheConfig(name = "dcache", userBits = DcacheUserBundleWidth)) 168 169} 170