1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.cache.mmu._ 31import xiangshan.frontend._ 32import xiangshan.mem.L1PrefetchFuzzer 33 34abstract class XSModule(implicit val p: Parameters) extends Module 35 with HasXSParameter 36 with HasFPUParameters 37 38//remove this trait after impl module logic 39trait NeedImpl { 40 this: RawModule => 41 protected def IO[T <: Data](iodef: T): T = { 42 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 43 val io = chisel3.experimental.IO(iodef) 44 io <> DontCare 45 io 46 } 47} 48 49abstract class XSBundle(implicit val p: Parameters) extends Bundle 50 with HasXSParameter 51 52abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 53 with HasXSParameter 54{ 55 override def shouldBeInlined: Boolean = false 56 // interrupt sinks 57 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 58 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 59 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 60 // outer facing nodes 61 val frontend = LazyModule(new Frontend()) 62 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 63 val backend = LazyModule(new Backend(backendParams)) 64 65 val memBlock = LazyModule(new MemBlock) 66} 67 68class XSCore()(implicit p: config.Parameters) extends XSCoreBase 69 with HasXSDts 70{ 71 lazy val module = new XSCoreImp(this) 72} 73 74class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 75 with HasXSParameter 76 with HasSoCParameter { 77 val io = IO(new Bundle { 78 val hartId = Input(UInt(64.W)) 79 val reset_vector = Input(UInt(PAddrBits.W)) 80 val cpu_halt = Output(Bool()) 81 val l2_pf_enable = Output(Bool()) 82 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 83 val beu_errors = Output(new XSL1BusErrors()) 84 val l2_hint = Input(Valid(new L2ToL1Hint())) 85 val l2PfqBusy = Input(Bool()) 86 val debugTopDown = new Bundle { 87 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 88 val l2MissMatch = Input(Bool()) 89 val l3MissMatch = Input(Bool()) 90 } 91 }) 92 93 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 94 95 val frontend = outer.frontend.module 96 val backend = outer.backend.module 97 val memBlock = outer.memBlock.module 98 99 val fenceio = backend.io.fenceio 100 fenceio.disableSfence := DontCare 101 102 frontend.io.hartId := io.hartId 103 frontend.io.backend <> backend.io.frontend 104 frontend.io.sfence <> backend.io.frontendSfence 105 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 106 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 107 frontend.io.fencei <> fenceio.fencei 108 109 backend.io.fromTop.hartId := io.hartId 110 backend.io.fromTop.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 111 backend.io.fromTop.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 112 backend.io.fromTop.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 113 backend.io.fromTop.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 114 backend.io.fromTop.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 115 116 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 117 118 backend.io.mem.stIn.zip(memBlock.io.stIn).foreach { case (sink, source) => 119 sink.valid := source.valid 120 sink.bits := 0.U.asTypeOf(sink.bits) 121 sink.bits.robIdx := source.bits.uop.robIdx 122 sink.bits.ssid := source.bits.uop.ssid 123 sink.bits.storeSetHit := source.bits.uop.storeSetHit 124 // The other signals have not been used 125 } 126 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 127 backend.io.mem.lsqEnqIO <> memBlock.io.enqLsq 128 backend.io.mem.sqDeq := memBlock.io.sqDeq 129 backend.io.mem.lqDeq := memBlock.io.lqDeq 130 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 131 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 132 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 133 backend.io.mem.stIssuePtr := memBlock.io.stIssuePtr 134 backend.io.mem.ldaIqFeedback <> memBlock.io.ldaIqFeedback 135 backend.io.mem.staIqFeedback <> memBlock.io.staIqFeedback 136 backend.io.mem.ldCancel <> memBlock.io.ldCancel 137 backend.io.mem.writeBack.zipAll(memBlock.io.writeback, DontCare, DontCare).foreach { case (back, mem) => 138 back <> mem 139 } // TODO: replace zipAll with zip when vls is fully implemented 140 141 frontend.io.reset_vector := io.reset_vector 142 143 io.cpu_halt := backend.io.toTop.cpuHalted 144 145 // memblock error exception writeback, 1 cycle after normal writeback 146 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 147 148 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 149 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 150 io.beu_errors.l2 <> DontCare 151 152 memBlock.io.hartId := io.hartId 153 memBlock.io.issue.zipAll(backend.io.mem.issueUops, DontCare, DontCare).foreach { case(memIssue, backIssue) => 154 backIssue <> memIssue 155 } // TODO: replace zipAll with zip when vls is fully implemented 156 // By default, instructions do not have exceptions when they enter the function units. 157 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 158 memBlock.io.loadPc := backend.io.mem.loadPcRead 159 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 160 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 161 backend.io.mem.exceptionVAddr := memBlock.io.lsqio.exceptionAddr.vaddr 162 backend.io.mem.csrDistributedUpdate := memBlock.io.csrUpdate 163 backend.io.mem.debugLS := memBlock.io.debug_ls 164 backend.io.mem.lsTopdownInfo := memBlock.io.lsTopdownInfo 165 backend.io.mem.lqCanAccept := memBlock.io.lsqio.lqCanAccept 166 backend.io.mem.sqCanAccept := memBlock.io.lsqio.sqCanAccept 167 168 backend.io.perf.frontendInfo := frontend.io.frontendInfo 169 backend.io.perf.memInfo := memBlock.io.memInfo 170 backend.io.perf.perfEventsFrontend := frontend.getPerf 171 backend.io.perf.perfEventsLsu := memBlock.getPerf 172 backend.io.perf.perfEventsHc := io.perfEvents 173 backend.io.perf.perfEventsCtrl := DontCare 174 backend.io.perf.retiredInstr := DontCare 175 backend.io.perf.ctrlInfo := DontCare 176 177 memBlock.io.sfence <> backend.io.mem.sfence 178 memBlock.io.fenceToSbuffer <> backend.io.fenceio.sbuffer 179 180 memBlock.io.redirect <> backend.io.mem.redirect 181 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 182 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 183 memBlock.io.lsqio.rob <> backend.io.mem.robLsqIO 184 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 185 memBlock.io.itlb <> frontend.io.ptw 186 memBlock.io.l2_hint.valid := io.l2_hint.valid 187 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 188 memBlock.io.l2PfqBusy := io.l2PfqBusy 189 memBlock.io.int2vlsu <> DontCare 190 memBlock.io.vec2vlsu <> DontCare 191 memBlock.io.vlsu2vec <> DontCare 192 memBlock.io.vlsu2int <> DontCare 193 memBlock.io.vlsu2ctrl <> DontCare 194 195 // TODO: Connect us when implemented 196 memBlock.io.int2vlsu <> DontCare 197 memBlock.io.vec2vlsu <> DontCare 198 memBlock.io.vlsu2vec <> DontCare 199 memBlock.io.vlsu2int <> DontCare 200 memBlock.io.vlsu2ctrl <> DontCare 201 202 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 203 io.l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 204 205 // top-down info 206 memBlock.io.debugTopDown.robHeadVaddr := ctrlBlock.io.debugTopDown.fromRob.robHeadVaddr 207 frontend.io.debugTopDown.robHeadVaddr := ctrlBlock.io.debugTopDown.fromRob.robHeadVaddr 208 io.debugTopDown.robHeadPaddr := ctrlBlock.io.debugTopDown.fromRob.robHeadPaddr 209 ctrlBlock.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 210 ctrlBlock.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 211 ctrlBlock.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 212 memBlock.io.debugRolling := ctrlBlock.io.debugRolling 213 214 // Modules are reset one by one 215 val resetTree = ResetGenNode( 216 Seq( 217 ModuleNode(memBlock), 218 ResetGenNode(Seq( 219 ModuleNode(backend), 220 ResetGenNode(Seq( 221 ResetGenNode(Seq( 222 ModuleNode(frontend) 223 )) 224 )) 225 )) 226 ) 227 ) 228 229 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 230 231} 232