1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DP1Parameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend.Frontend 11import xiangshan.mem._ 12import utils._ 13 14trait HasXSParameter { 15 val XLEN = 64 16 val HasMExtension = true 17 val HasCExtension = true 18 val HasDiv = true 19 val HasIcache = true 20 val HasDcache = true 21 val EnableStoreQueue = false 22 val AddrBits = 64 // AddrBits is used in some cases 23 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 24 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 25 val AddrBytes = AddrBits / 8 // unused 26 val DataBits = XLEN 27 val DataBytes = DataBits / 8 28 val CacheLineSize = 512 29 val SbufferSize = 16 30 val HasFPU = true 31 val FetchWidth = 8 32 val IBufSize = 64 33 val DecodeWidth = 6 34 val RenameWidth = 6 35 val CommitWidth = 6 36 val BrqSize = 16 37 val IssQueSize = 8 38 val BrTagWidth = log2Up(BrqSize) 39 val NRPhyRegs = 128 40 val PhyRegIdxWidth = log2Up(NRPhyRegs) 41 val NRReadPorts = 14 42 val NRWritePorts = 8 43 val RoqSize = 32 44 val MoqSize = 16 // 64 45 val InnerRoqIdxWidth = log2Up(RoqSize) 46 val RoqIdxWidth = InnerRoqIdxWidth + 1 47 val InnerMoqIdxWidth = log2Up(MoqSize) 48 val MoqIdxWidth = InnerMoqIdxWidth + 1 49 val IntDqDeqWidth = 4 50 val FpDqDeqWidth = 4 51 val LsDqDeqWidth = 4 52 val dp1Paremeters = DP1Parameters( 53 IntDqSize = 16, 54 FpDqSize = 16, 55 LsDqSize = 16 56 ) 57 val exuParameters = ExuParameters( 58 JmpCnt = 1, 59 AluCnt = 4, 60 MulCnt = 1, 61 MduCnt = 1, 62 FmacCnt = 0, 63 FmiscCnt = 0, 64 FmiscDivSqrtCnt = 0, 65 LduCnt = 0, 66 StuCnt = 1 67 ) 68} 69 70trait HasXSLog { this: Module => 71 implicit val moduleName: String = this.name 72} 73 74abstract class XSModule extends Module 75 with HasXSParameter 76 with HasExceptionNO 77 with HasXSLog 78 79//remove this trait after impl module logic 80trait NeedImpl { this: Module => 81 override protected def IO[T <: Data](iodef: T): T = { 82 val io = chisel3.experimental.IO(iodef) 83 io <> DontCare 84 io 85 } 86} 87 88abstract class XSBundle extends Bundle 89 with HasXSParameter 90 91case class XSConfig 92( 93 FPGAPlatform: Boolean = true, 94 EnableDebug: Boolean = true 95) 96 97object AddressSpace extends HasXSParameter { 98 // (start, size) 99 // address out of MMIO will be considered as DRAM 100 def mmio = List( 101 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 102 (0x40000000L, 0x40000000L) // external devices 103 ) 104 105 def isMMIO(addr: UInt): Bool = mmio.map(range => { 106 require(isPow2(range._2)) 107 val bits = log2Up(range._2) 108 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 109 }).reduce(_ || _) 110} 111 112 113class XSCore(implicit p: XSConfig) extends XSModule { 114 val io = IO(new Bundle { 115 val imem = new SimpleBusC 116 val dmem = new SimpleBusC 117 val mmio = new SimpleBusUC 118 val frontend = Flipped(new SimpleBusUC()) 119 }) 120 121 io.imem <> DontCare 122 123 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 124 125 val front = Module(new Frontend) 126 val backend = Module(new Backend) 127 val mem = Module(new MemPipeline) 128 129 mem.io := DontCare // FIXME 130 131 front.io.backend <> backend.io.frontend 132 133 backend.io.memMMU.imem <> DontCare 134 135 val dtlb = TLB( 136 in = backend.io.dmem, 137 mem = dmemXbar.io.in(1), 138 flush = false.B, 139 csrMMU = backend.io.memMMU.dmem 140 )(TLBConfig(name = "dtlb", totalEntry = 64)) 141 dmemXbar.io.in(0) <> dtlb.io.out 142 dmemXbar.io.in(2) <> io.frontend 143 144 io.dmem <> Cache( 145 in = dmemXbar.io.out, 146 mmio = Seq(io.mmio), 147 flush = "b00".U, 148 empty = dtlb.io.cacheEmpty, 149 enable = HasDcache 150 )(CacheConfig(name = "dcache")) 151 152 XSDebug("(req valid, ready | resp valid, ready) \n") 153 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 154 io.dmem.mem.req.valid, 155 io.dmem.mem.req.ready, 156 io.dmem.mem.req.bits.addr, 157 io.dmem.mem.resp.valid, 158 io.dmem.mem.resp.ready, 159 io.dmem.coh.req.valid, 160 io.dmem.coh.req.ready, 161 io.dmem.coh.req.bits.addr, 162 io.dmem.coh.resp.valid, 163 io.dmem.coh.resp.ready, 164 dmemXbar.io.out.req.valid, 165 dmemXbar.io.out.req.ready, 166 dmemXbar.io.out.req.bits.addr, 167 dmemXbar.io.out.resp.valid, 168 dmemXbar.io.out.resp.ready, 169 backend.io.dmem.req.valid, 170 backend.io.dmem.req.ready, 171 backend.io.dmem.req.bits.addr, 172 backend.io.dmem.resp.valid, 173 backend.io.dmem.resp.ready 174 ) 175} 176