1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import device.MsiInfoBundle 24import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.cache.mmu._ 31import xiangshan.frontend._ 32import xiangshan.mem.L1PrefetchFuzzer 33import scala.collection.mutable.ListBuffer 34import xiangshan.cache.mmu.TlbRequestIO 35 36abstract class XSModule(implicit val p: Parameters) extends Module 37 with HasXSParameter 38 with HasFPUParameters 39 40//remove this trait after impl module logic 41trait NeedImpl { 42 this: RawModule => 43 protected def IO[T <: Data](iodef: T): T = { 44 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 45 val io = chisel3.IO(iodef) 46 io <> DontCare 47 io 48 } 49} 50 51abstract class XSBundle(implicit val p: Parameters) extends Bundle 52 with HasXSParameter 53 54abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 55 with HasXSParameter 56{ 57 override def shouldBeInlined: Boolean = false 58 // outer facing nodes 59 val frontend = LazyModule(new Frontend()) 60 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 61 val backend = LazyModule(new Backend(backendParams)) 62 63 val memBlock = LazyModule(new MemBlock) 64 65 memBlock.frontendBridge.icache_node := frontend.icache.clientNode 66 memBlock.frontendBridge.instr_uncache_node := frontend.instrUncache.clientNode 67} 68 69class XSCore()(implicit p: config.Parameters) extends XSCoreBase 70 with HasXSDts 71{ 72 lazy val module = new XSCoreImp(this) 73} 74 75class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 76 with HasXSParameter 77 with HasSoCParameter { 78 val io = IO(new Bundle { 79 val hartId = Input(UInt(hartIdLen.W)) 80 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 81 val reset_vector = Input(UInt(PAddrBits.W)) 82 val cpu_halt = Output(Bool()) 83 val l2_pf_enable = Output(Bool()) 84 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 85 val beu_errors = Output(new XSL1BusErrors()) 86 val l2_hint = Input(Valid(new L2ToL1Hint())) 87 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 88 val l2PfqBusy = Input(Bool()) 89 val debugTopDown = new Bundle { 90 val robTrueCommit = Output(UInt(64.W)) 91 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 92 val l2MissMatch = Input(Bool()) 93 val l3MissMatch = Input(Bool()) 94 } 95 }) 96 97 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 98 99 val frontend = outer.frontend.module 100 val backend = outer.backend.module 101 val memBlock = outer.memBlock.module 102 103 frontend.io.hartId := memBlock.io.inner_hartId 104 frontend.io.reset_vector := memBlock.io.inner_reset_vector 105 frontend.io.backend <> backend.io.frontend 106 frontend.io.sfence <> backend.io.frontendSfence 107 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 108 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 109 frontend.io.fencei <> backend.io.fenceio.fencei 110 111 backend.io.fromTop.hartId := memBlock.io.inner_hartId 112 backend.io.fromTop.msiInfo := io.msiInfo 113 backend.io.fromTop.externalInterrupt := memBlock.io.externalInterrupt 114 115 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 116 117 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 118 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 119 sink.valid := source.valid 120 sink.bits := 0.U.asTypeOf(sink.bits) 121 sink.bits.robIdx := source.bits.uop.robIdx 122 sink.bits.ssid := source.bits.uop.ssid 123 sink.bits.storeSetHit := source.bits.uop.storeSetHit 124 // The other signals have not been used 125 } 126 backend.io.mem.memoryViolation <> memBlock.io.mem_to_ooo.memoryViolation 127 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 128 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 129 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 130 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 131 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 132 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 133 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 134 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 135 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 136 backend.io.mem.ldaIqFeedback <> memBlock.io.mem_to_ooo.ldaIqFeedback 137 backend.io.mem.staIqFeedback <> memBlock.io.mem_to_ooo.staIqFeedback 138 backend.io.mem.hyuIqFeedback <> memBlock.io.mem_to_ooo.hyuIqFeedback 139 backend.io.mem.vstuIqFeedback <> memBlock.io.mem_to_ooo.vstuIqFeedback 140 backend.io.mem.vlduIqFeedback <> memBlock.io.mem_to_ooo.vlduIqFeedback 141 backend.io.mem.ldCancel <> memBlock.io.mem_to_ooo.ldCancel 142 backend.io.mem.wakeup <> memBlock.io.mem_to_ooo.wakeup 143 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 144 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 145 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 146 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 147 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 148 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 149 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 150 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 151 152 // memblock error exception writeback, 1 cycle after normal writeback 153 backend.io.mem.s3_delayed_load_error <> memBlock.io.mem_to_ooo.s3_delayed_load_error 154 155 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 156 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 157 backend.io.mem.csrDistributedUpdate := memBlock.io.mem_to_ooo.csrUpdate 158 backend.io.mem.debugLS := memBlock.io.debug_ls 159 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 160 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 161 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 162 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 163 // Todo: remove it 164 backend.io.fenceio.disableSfence := DontCare 165 backend.io.fenceio.disableHfencev := DontCare 166 backend.io.fenceio.disableHfenceg := DontCare 167 backend.io.fenceio.virtMode := DontCare 168 169 backend.io.perf.frontendInfo := frontend.io.frontendInfo 170 backend.io.perf.memInfo := memBlock.io.memInfo 171 backend.io.perf.perfEventsFrontend := frontend.getPerf 172 backend.io.perf.perfEventsLsu := memBlock.getPerf 173 backend.io.perf.perfEventsHc := io.perfEvents 174 backend.io.perf.perfEventsCtrl := DontCare 175 backend.io.perf.retiredInstr := DontCare 176 backend.io.perf.ctrlInfo := DontCare 177 178 // top -> memBlock 179 memBlock.io.hartId := io.hartId 180 memBlock.io.outer_reset_vector := io.reset_vector 181 // frontend -> memBlock 182 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 183 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 184 memBlock.io.inner_cpu_halt := backend.io.toTop.cpuHalted 185 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 186 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 187 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 188 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 189 backend.io.mem.issueHysta.map(_.ready := false.B) // this fake port should not be used 190 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 191 192 // By default, instructions do not have exceptions when they enter the function units. 193 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 194 memBlock.io.ooo_to_mem.loadPc := backend.io.mem.loadPcRead 195 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 196 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 197 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 198 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 199 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 200 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 201 202 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 203 204 memBlock.io.redirect <> backend.io.mem.redirect 205 memBlock.io.ooo_to_mem.csrCtrl <> backend.io.mem.csrCtrl 206 memBlock.io.ooo_to_mem.tlbCsr <> backend.io.mem.tlbCsr 207 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 208 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 209 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 210 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 211 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 212 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 213 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 214 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 215 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 216 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 217 218 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 219 memBlock.io.l2_hint.valid := io.l2_hint.valid 220 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 221 memBlock.io.l2_tlb_req <> io.l2_tlb_req 222 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 223 memBlock.io.l2PfqBusy := io.l2PfqBusy 224 225 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 226 227 // top-down info 228 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 229 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 230 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 231 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 232 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 233 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 234 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 235 memBlock.io.debugRolling := backend.io.debugRolling 236 237 io.cpu_halt := memBlock.io.outer_cpu_halt 238 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 239 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 240 io.beu_errors.l2 <> DontCare 241 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 242 // Modules are reset one by one 243 val resetTree = ResetGenNode( 244 Seq( 245 ModuleNode(memBlock), 246 ResetGenNode(Seq( 247 ModuleNode(backend), 248 ResetGenNode(Seq( 249 ResetGenNode(Seq( 250 ModuleNode(frontend) 251 )) 252 )) 253 )) 254 ) 255 ) 256 257 // ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 258 if (debugOpts.ResetGen) { 259 frontend.reset := memBlock.reset_io_frontend 260 backend.reset := memBlock.reset_io_backend 261 } 262} 263