xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 3e60c71712d88118db28a3b712d654334153e247) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Config
9import xiangshan.backend.exu.ExuConfig
10import xiangshan.frontend.Frontend
11import xiangshan.utils._
12
13trait HasXSParameter {
14  val XLEN = 64
15  val HasMExtension = true
16  val HasCExtension = true
17  val HasDiv = true
18  val HasIcache = true
19  val HasDcache = true
20  val EnableStoreQueue = false
21  val AddrBits = 64 // AddrBits is used in some cases
22  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
23  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
24  val AddrBytes = AddrBits / 8 // unused
25  val DataBits = XLEN
26  val DataBytes = DataBits / 8
27  val HasFPU = true
28  val FetchWidth = 8
29  val IBufSize = 64
30  val DecodeWidth = 6
31  val RenameWidth = 6
32  val CommitWidth = 6
33  val BrqSize = 16
34  val BrTagWidth = log2Up(BrqSize)
35  val NRPhyRegs = 128
36  val PhyRegIdxWidth = log2Up(NRPhyRegs)
37  val NRReadPorts = 14
38  val NRWritePorts = 8
39  val RoqSize = 32
40  val RoqIdxWidth = log2Up(RoqSize)
41  val ExtendedRoqIdxWidth = RoqIdxWidth + 1
42  val IntDqDeqWidth = 4
43  val FpDqDeqWidth = 4
44  val LsDqDeqWidth = 4
45  val dp1Config = DP1Config(
46    IntDqSize = 16,
47    FpDqSize = 16,
48    LsDqSize = 16
49  )
50  val exuConfig = ExuConfig(
51    AluCnt = 4,
52    BruCnt = 1,
53    MulCnt = 0,
54    MduCnt = 0,
55    FmacCnt = 0,
56    FmiscCnt = 0,
57    FmiscDivSqrtCnt = 0,
58    LduCnt = 1,
59    StuCnt = 0
60  )
61}
62
63trait HasXSLog { this: Module =>
64  implicit val moduleName: String = this.name
65}
66
67abstract class XSModule extends Module
68  with HasXSParameter
69  with HasExceptionNO
70  with HasXSLog
71
72//remove this trait after impl module logic
73trait NeedImpl { this: Module =>
74  override protected def IO[T <: Data](iodef: T): T = {
75    val io = chisel3.experimental.IO(iodef)
76    io <> DontCare
77    io
78  }
79}
80
81abstract class XSBundle extends Bundle
82  with HasXSParameter
83
84case class XSConfig
85(
86  FPGAPlatform: Boolean = true,
87  EnableDebug: Boolean = false
88)
89
90class XSCore(implicit val p: XSConfig) extends XSModule {
91  val io = IO(new Bundle {
92    val imem = new SimpleBusC
93    val dmem = new SimpleBusC
94    val mmio = new SimpleBusUC
95    val frontend = Flipped(new SimpleBusUC())
96  })
97
98  io.imem <> DontCare
99
100  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
101
102  val front = Module(new Frontend)
103  val backend = Module(new Backend)
104
105  front.io.backend <> backend.io.frontend
106
107  backend.io.memMMU.imem <> DontCare
108
109  val dtlb = TLB(
110    in = backend.io.dmem,
111    mem = dmemXbar.io.in(1),
112    flush = false.B,
113    csrMMU = backend.io.memMMU.dmem
114  )(TLBConfig(name = "dtlb", totalEntry = 64))
115  dmemXbar.io.in(0) <> dtlb.io.out
116  dmemXbar.io.in(2) <> io.frontend
117
118  io.dmem <> Cache(
119    in = dmemXbar.io.out,
120    mmio = Seq(io.mmio),
121    flush = "b00".U,
122    empty = dtlb.io.cacheEmpty,
123    enable = HasDcache
124  )(CacheConfig(name = "dcache"))
125}
126