xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 3e254c8b92f1e43fd440656dd134568c05a48f37) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Config
9import xiangshan.backend.exu.ExuConfig
10import xiangshan.frontend.Frontend
11
12trait HasXSParameter {
13  val XLEN = 64
14  val HasMExtension = true
15  val HasCExtension = true
16  val HasDiv = true
17  val HasIcache = true
18  val HasDcache = true
19  val EnableStoreQueue = false
20  val AddrBits = 64 // AddrBits is used in some cases
21  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
22  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
23  val AddrBytes = AddrBits / 8 // unused
24  val DataBits = XLEN
25  val DataBytes = DataBits / 8
26  val HasFPU = true
27  val FetchWidth = 8
28  val IBufSize = 64
29  val DecodeWidth = 8
30  val DecBufSize = 8
31  val RenameWidth = 6
32  val CommitWidth = 6
33  val BrqSize = 16
34  val BrTagWidth = log2Up(BrqSize)
35  val NRPhyRegs = 96
36  val PhyRegIdxWidth = log2Up(NRPhyRegs)
37  val NRReadPorts = 14
38  val NRWritePorts = 8
39  val RoqSize = 128
40  val RoqIdxWidth = log2Up(RoqSize)
41  val IntDqDeqWidth = 4
42  val FpDqDeqWidth = 4
43  val LsDqDeqWidth = 4
44  val dp1Config = DP1Config(
45    IntDqSize = 16,
46    FpDqSize = 16,
47    LsDqSize = 16
48  )
49  val exuConfig = ExuConfig(
50    AluCnt = 4,
51    BruCnt = 1,
52    MulCnt = 1,
53    MduCnt = 1,
54    FmacCnt = 4,
55    FmiscCnt = 1,
56    FmiscDivSqrtCnt = 1,
57    LduCnt = 1,
58    StuCnt = 1
59  )
60}
61
62abstract class XSModule extends Module
63  with HasXSParameter
64  with HasExceptionNO
65
66//remove this trait after impl module logic
67trait NeedImpl { this: Module =>
68  override protected def IO[T <: Data](iodef: T): T = {
69    val io = chisel3.experimental.IO(iodef)
70    io <> DontCare
71    io
72  }
73}
74
75abstract class XSBundle extends Bundle
76  with HasXSParameter
77
78case class XSConfig
79(
80  FPGAPlatform: Boolean = true,
81  EnableDebug: Boolean = false
82)
83
84class XSCore(implicit val p: XSConfig) extends XSModule {
85  val io = IO(new Bundle {
86    val imem = new SimpleBusC
87    val dmem = new SimpleBusC
88    val mmio = new SimpleBusUC
89    val frontend = Flipped(new SimpleBusUC())
90  })
91
92  io.imem <> DontCare
93
94  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
95
96  val front = Module(new Frontend)
97  val backend = Module(new Backend)
98
99  front.io.backend <> backend.io.frontend
100
101  backend.io.memMMU.imem <> DontCare
102
103  val dtlb = TLB(
104    in = backend.io.dmem,
105    mem = dmemXbar.io.in(1),
106    flush = false.B,
107    csrMMU = backend.io.memMMU.dmem
108  )(TLBConfig(name = "dtlb", totalEntry = 64))
109  dmemXbar.io.in(0) <> dtlb.io.out
110  dmemXbar.io.in(2) <> io.frontend
111
112  io.dmem <> Cache(
113    in = dmemXbar.io.out,
114    mmio = Seq(io.mmio),
115    flush = "b00".U,
116    empty = dtlb.io.cacheEmpty,
117    enable = HasDcache
118  )(CacheConfig(name = "dcache"))
119}
120