xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 3b89a9dccfa086144d3336275b29d81093a7b805) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import top.Parameters
6import xiangshan.backend._
7import xiangshan.backend.dispatch.DispatchParameters
8import xiangshan.backend.exu.ExuParameters
9import xiangshan.backend.exu.Exu._
10import xiangshan.frontend._
11import xiangshan.mem._
12import xiangshan.backend.fu.HasExceptionNO
13import xiangshan.cache.{DCache, InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater, Uncache, MemoryOpConstants, MissReq}
14import xiangshan.cache.prefetch._
15import chipsalliance.rocketchip.config
16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar}
18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker}
21import freechips.rocketchip.tile.HasFPUParameters
22import sifive.blocks.inclusivecache.PrefetcherIO
23import utils._
24
25object hartIdCore extends (() => Int) {
26  var x = 0
27
28  def apply(): Int = {
29    x = x + 1
30    x - 1
31  }
32}
33
34case class XSCoreParameters
35(
36  XLEN: Int = 64,
37  HasMExtension: Boolean = true,
38  HasCExtension: Boolean = true,
39  HasDiv: Boolean = true,
40  HasICache: Boolean = true,
41  HasDCache: Boolean = true,
42  EnableStoreQueue: Boolean = true,
43  AddrBits: Int = 64,
44  VAddrBits: Int = 39,
45  PAddrBits: Int = 40,
46  HasFPU: Boolean = true,
47  FectchWidth: Int = 8,
48  EnableBPU: Boolean = true,
49  EnableBPD: Boolean = true,
50  EnableRAS: Boolean = true,
51  EnableLB: Boolean = false,
52  EnableLoop: Boolean = true,
53  EnableSC: Boolean = false,
54  EnbaleTlbDebug: Boolean = false,
55  EnableJal: Boolean = false,
56  EnableUBTB: Boolean = true,
57  HistoryLength: Int = 64,
58  BtbSize: Int = 2048,
59  JbtacSize: Int = 1024,
60  JbtacBanks: Int = 8,
61  RasSize: Int = 16,
62  CacheLineSize: Int = 512,
63  UBtbWays: Int = 16,
64  BtbWays: Int = 2,
65
66  EnableL1plusPrefetcher: Boolean = true,
67  IBufSize: Int = 32,
68  DecodeWidth: Int = 6,
69  RenameWidth: Int = 6,
70  CommitWidth: Int = 6,
71  BrqSize: Int = 32,
72  FtqSize: Int = 48,
73  IssQueSize: Int = 12,
74  NRPhyRegs: Int = 160,
75  NRIntReadPorts: Int = 14,
76  NRIntWritePorts: Int = 8,
77  NRFpReadPorts: Int = 14,
78  NRFpWritePorts: Int = 8,
79  LoadQueueSize: Int = 64,
80  StoreQueueSize: Int = 48,
81  RoqSize: Int = 192,
82  dpParams: DispatchParameters = DispatchParameters(
83    IntDqSize = 16,
84    FpDqSize = 16,
85    LsDqSize = 16,
86    IntDqDeqWidth = 4,
87    FpDqDeqWidth = 4,
88    LsDqDeqWidth = 4
89  ),
90  exuParameters: ExuParameters = ExuParameters(
91    JmpCnt = 1,
92    AluCnt = 4,
93    MulCnt = 0,
94    MduCnt = 2,
95    FmacCnt = 4,
96    FmiscCnt = 2,
97    FmiscDivSqrtCnt = 0,
98    LduCnt = 2,
99    StuCnt = 2
100  ),
101  LoadPipelineWidth: Int = 2,
102  StorePipelineWidth: Int = 2,
103  StoreBufferSize: Int = 16,
104  RefillSize: Int = 512,
105  TlbEntrySize: Int = 32,
106  TlbSPEntrySize: Int = 4,
107  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
108  PtwSPEntrySize: Int = 16,
109  PtwL1EntrySize: Int = 16,
110  PtwL2EntrySize: Int = 2048, //(256 * 8)
111  NumPerfCounters: Int = 16,
112  NrExtIntr: Int = 150
113)
114
115trait HasXSParameter {
116
117  val core = Parameters.get.coreParameters
118  val env = Parameters.get.envParameters
119
120  val XLEN = 64
121  val minFLen = 32
122  val fLen = 64
123
124  def xLen = 64
125
126  val HasMExtension = core.HasMExtension
127  val HasCExtension = core.HasCExtension
128  val HasDiv = core.HasDiv
129  val HasIcache = core.HasICache
130  val HasDcache = core.HasDCache
131  val EnableStoreQueue = core.EnableStoreQueue
132  val AddrBits = core.AddrBits // AddrBits is used in some cases
133  val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits
134  val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits
135  val AddrBytes = AddrBits / 8 // unused
136  val DataBits = XLEN
137  val DataBytes = DataBits / 8
138  val HasFPU = core.HasFPU
139  val FetchWidth = core.FectchWidth
140  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
141  val EnableBPU = core.EnableBPU
142  val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3
143  val EnableRAS = core.EnableRAS
144  val EnableLB = core.EnableLB
145  val EnableLoop = core.EnableLoop
146  val EnableSC = core.EnableSC
147  val EnbaleTlbDebug = core.EnbaleTlbDebug
148  val HistoryLength = core.HistoryLength
149  val BtbSize = core.BtbSize
150  // val BtbWays = 4
151  val BtbBanks = PredictWidth
152  // val BtbSets = BtbSize / BtbWays
153  val JbtacSize = core.JbtacSize
154  val JbtacBanks = core.JbtacBanks
155  val RasSize = core.RasSize
156  val CacheLineSize = core.CacheLineSize
157  val CacheLineHalfWord = CacheLineSize / 16
158  val ExtHistoryLength = HistoryLength + 64
159  val UBtbWays = core.UBtbWays
160  val BtbWays = core.BtbWays
161  val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher
162  val IBufSize = core.IBufSize
163  val DecodeWidth = core.DecodeWidth
164  val RenameWidth = core.RenameWidth
165  val CommitWidth = core.CommitWidth
166  val BrqSize = core.BrqSize
167  val FtqSize = core.FtqSize
168  val IssQueSize = core.IssQueSize
169  val BrTagWidth = log2Up(BrqSize)
170  val NRPhyRegs = core.NRPhyRegs
171  val PhyRegIdxWidth = log2Up(NRPhyRegs)
172  val RoqSize = core.RoqSize
173  val LoadQueueSize = core.LoadQueueSize
174  val StoreQueueSize = core.StoreQueueSize
175  val dpParams = core.dpParams
176  val exuParameters = core.exuParameters
177  val NRIntReadPorts = core.NRIntReadPorts
178  val NRIntWritePorts = core.NRIntWritePorts
179  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
180  val NRFpReadPorts = core.NRFpReadPorts
181  val NRFpWritePorts = core.NRFpWritePorts
182  val LoadPipelineWidth = core.LoadPipelineWidth
183  val StorePipelineWidth = core.StorePipelineWidth
184  val StoreBufferSize = core.StoreBufferSize
185  val RefillSize = core.RefillSize
186  val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth
187  val TlbEntrySize = core.TlbEntrySize
188  val TlbSPEntrySize = core.TlbSPEntrySize
189  val PtwL3EntrySize = core.PtwL3EntrySize
190  val PtwSPEntrySize = core.PtwSPEntrySize
191  val PtwL1EntrySize = core.PtwL1EntrySize
192  val PtwL2EntrySize = core.PtwL2EntrySize
193  val NumPerfCounters = core.NumPerfCounters
194  val NrExtIntr = core.NrExtIntr
195
196  val instBytes = if (HasCExtension) 2 else 4
197  val instOffsetBits = log2Ceil(instBytes)
198
199  val icacheParameters = ICacheParameters(
200    tagECC = Some("parity"),
201    dataECC = Some("parity"),
202    replacer = Some("setlru"),
203    nMissEntries = 2
204  )
205
206  val l1plusCacheParameters = L1plusCacheParameters(
207    tagECC = Some("secded"),
208    dataECC = Some("secded"),
209    nMissEntries = 8
210  )
211
212  val dcacheParameters = DCacheParameters(
213    tagECC = Some("secded"),
214    dataECC = Some("secded"),
215    nMissEntries = 16,
216    nProbeEntries = 16,
217    nReleaseEntries = 16,
218    nStoreReplayEntries = 16
219  )
220
221  val LRSCCycles = 100
222
223
224  // cache hierarchy configurations
225  val l1BusDataWidth = 256
226
227  // L2 configurations
228  val L1BusWidth = 256
229  val L2Size = 512 * 1024 // 512KB
230  val L2BlockSize = 64
231  val L2NWays = 8
232  val L2NSets = L2Size / L2BlockSize / L2NWays
233
234  // L3 configurations
235  val L2BusWidth = 256
236  val L3Size = 4 * 1024 * 1024 // 4MB
237  val L3BlockSize = 64
238  val L3NBanks = 4
239  val L3NWays = 8
240  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
241
242  // on chip network configurations
243  val L3BusWidth = 256
244
245  // icache prefetcher
246  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
247    enable = true,
248    _type = "stream",
249    streamParams = StreamPrefetchParameters(
250      streamCnt = 2,
251      streamSize = 4,
252      ageWidth = 4,
253      blockBytes = l1plusCacheParameters.blockBytes,
254      reallocStreamOnMissInstantly = true,
255      cacheName = "icache"
256    )
257  )
258
259  // dcache prefetcher
260  val l2PrefetcherParameters = L2PrefetcherParameters(
261    enable = true,
262    _type = "bop", // "stream" or "bop"
263    streamParams = StreamPrefetchParameters(
264      streamCnt = 4,
265      streamSize = 4,
266      ageWidth = 4,
267      blockBytes = L2BlockSize,
268      reallocStreamOnMissInstantly = true,
269      cacheName = "dcache"
270    ),
271    bopParams = BOPParameters(
272      rrTableEntries = 256,
273      rrTagBits = 12,
274      scoreBits = 5,
275      roundMax = 50,
276      badScore = 1,
277      blockBytes = L2BlockSize,
278      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
279    ),
280  )
281}
282
283trait HasXSLog {
284  this: RawModule =>
285  implicit val moduleName: String = this.name
286}
287
288abstract class XSModule extends MultiIOModule
289  with HasXSParameter
290  with HasExceptionNO
291  with HasXSLog
292  with HasFPUParameters {
293  def io: Record
294}
295
296//remove this trait after impl module logic
297trait NeedImpl {
298  this: RawModule =>
299  override protected def IO[T <: Data](iodef: T): T = {
300    println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module")
301    val io = chisel3.experimental.IO(iodef)
302    io <> DontCare
303    io
304  }
305}
306
307abstract class XSBundle extends Bundle
308  with HasXSParameter
309
310case class EnviromentParameters
311(
312  FPGAPlatform: Boolean = true,
313  EnableDebug: Boolean = false,
314  EnablePerfDebug: Boolean = false,
315  DualCore: Boolean = false
316)
317
318// object AddressSpace extends HasXSParameter {
319//   // (start, size)
320//   // address out of MMIO will be considered as DRAM
321//   def mmio = List(
322//     (0x00000000L, 0x40000000L),  // internal devices, such as CLINT and PLIC
323//     (0x40000000L, 0x40000000L)   // external devices
324//   )
325
326//   def isMMIO(addr: UInt): Bool = mmio.map(range => {
327//     require(isPow2(range._2))
328//     val bits = log2Up(range._2)
329//     (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
330//   }).reduce(_ || _)
331// }
332
333
334class XSCore()(implicit p: config.Parameters) extends LazyModule
335  with HasXSParameter
336  with HasExeBlockHelper {
337  // outer facing nodes
338  val frontend = LazyModule(new Frontend())
339  val l1pluscache = LazyModule(new L1plusCache())
340  val ptw = LazyModule(new PTW())
341  val l2Prefetcher = LazyModule(new L2Prefetcher())
342  val memBlock = LazyModule(new MemBlock(
343    fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency),
344    slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs,
345    fastWakeUpOut = Seq(),
346    slowWakeUpOut = loadExuConfigs
347  ))
348
349  lazy val module = new XSCoreImp(this)
350}
351
352class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
353  with HasXSParameter
354  with HasExeBlockHelper {
355  val io = IO(new Bundle {
356    val externalInterrupt = new ExternalInterruptIO
357    val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits))
358  })
359
360  val difftestIO = IO(new DifftestBundle())
361  difftestIO <> DontCare
362
363  val trapIO = IO(new TrapIO())
364  trapIO <> DontCare
365
366  println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
367  AddressSpace.checkMemmap()
368  AddressSpace.printMemmap()
369
370  // to fast wake up fp, mem rs
371  val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency)
372  val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency)
373
374  val ctrlBlock = Module(new CtrlBlock)
375  val integerBlock = Module(new IntegerBlock(
376    fastWakeUpIn = Seq(),
377    slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs,
378    fastWakeUpOut = intBlockFastWakeUp,
379    slowWakeUpOut = intBlockSlowWakeUp
380  ))
381  val floatBlock = Module(new FloatBlock(
382    fastWakeUpIn = Seq(),
383    slowWakeUpIn = intExuConfigs.filter(_.writeFpRf) ++ loadExuConfigs,
384    fastWakeUpOut = Seq(),
385    slowWakeUpOut = fpExuConfigs
386  ))
387
388  val frontend = outer.frontend.module
389  val memBlock = outer.memBlock.module
390  val l1pluscache = outer.l1pluscache.module
391  val ptw = outer.ptw.module
392  val l2Prefetcher = outer.l2Prefetcher.module
393
394  frontend.io.backend <> ctrlBlock.io.frontend
395  frontend.io.sfence <> integerBlock.io.fenceio.sfence
396  frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
397
398  frontend.io.icacheMemAcq <> l1pluscache.io.req
399  l1pluscache.io.resp <> frontend.io.icacheMemGrant
400  l1pluscache.io.flush := frontend.io.l1plusFlush
401  frontend.io.fencei := integerBlock.io.fenceio.fencei
402
403  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
404  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
405  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
406  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
407  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
408  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
409
410  val memBlockWakeUpInt = memBlock.io.wakeUpOut.slow.map(x => intOutValid(x))
411  val memBlockWakeUpFp = memBlock.io.wakeUpOut.slow.map(x => fpOutValid(x))
412  memBlock.io.wakeUpOut.slow.foreach(_.ready := true.B)
413
414  fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B)
415  val fpBlockWakeUpInt = fpExuConfigs
416    .zip(floatBlock.io.wakeUpOut.slow)
417    .filter(_._1.writeIntRf)
418    .map(_._2).map(x => intOutValid(x, connectReady = true))
419
420  intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B)
421  val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency)
422    .zip(integerBlock.io.wakeUpOut.slow)
423    .filter(_._1.writeFpRf)
424    .map(_._2).map(x => fpOutValid(x, connectReady = true))
425
426  integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt
427  integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
428
429  floatBlock.io.wakeUpIn.slow <> intBlockWakeUpFp ++ memBlockWakeUpFp
430  floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
431
432  val wakeUpMem = Seq(
433    integerBlock.io.wakeUpOut,
434    floatBlock.io.wakeUpOut,
435  )
436  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
437  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast)
438  // Note: 'WireInit' is used to block 'ready's from memBlock,
439  // we don't need 'ready's from memBlock
440  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x)))
441
442  integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags
443  integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
444  integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
445  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
446  integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet
447  integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
448  integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
449  integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
450  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
451  integerBlock.io.fenceio.sfence <> memBlock.io.sfence
452  integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
453  memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb
454
455  floatBlock.io.frm <> integerBlock.io.csrio.frm
456
457  memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
458  memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx
459  memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
460  memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType)
461
462  val itlbRepester = Module(new PTWRepeater())
463  val dtlbRepester = Module(new PTWRepeater())
464  itlbRepester.io.tlb <> frontend.io.ptw
465  dtlbRepester.io.tlb <> memBlock.io.ptw
466  itlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
467  dtlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
468  ptw.io.tlb(0) <> dtlbRepester.io.ptw
469  ptw.io.tlb(1) <> itlbRepester.io.ptw
470  ptw.io.sfence <> integerBlock.io.fenceio.sfence
471  ptw.io.csr <> integerBlock.io.csrio.tlb
472
473  val l2PrefetcherIn = Wire(Decoupled(new MissReq))
474  if (l2PrefetcherParameters.enable && l2PrefetcherParameters._type == "bop") {
475    l2PrefetcherIn.valid := io.l2ToPrefetcher.acquire.valid
476    l2PrefetcherIn.bits := DontCare
477    l2PrefetcherIn.bits.addr := io.l2ToPrefetcher.acquire.bits.address
478    l2PrefetcherIn.bits.cmd := Mux(io.l2ToPrefetcher.acquire.bits.write, MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD)
479  } else {
480    l2PrefetcherIn <> memBlock.io.toDCachePrefetch
481  }
482  l2Prefetcher.io.in <> l2PrefetcherIn
483
484  if (!env.FPGAPlatform) {
485    val id = hartIdCore()
486    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
487    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
488    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
489    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
490    difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic
491    difftestIO.fromPtw <> ptw.difftestIO
492    trapIO <> ctrlBlock.trapIO
493
494    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
495    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
496    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
497    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
498    difftestIO.fromXSCore.r := debugArchReg
499  }
500
501}
502