1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache,InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache, MemoryOpConstants, MissReq} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 21import freechips.rocketchip.tile.HasFPUParameters 22import sifive.blocks.inclusivecache.PrefetcherIO 23import utils._ 24 25case class XSCoreParameters 26( 27 XLEN: Int = 64, 28 HasMExtension: Boolean = true, 29 HasCExtension: Boolean = true, 30 HasDiv: Boolean = true, 31 HasICache: Boolean = true, 32 HasDCache: Boolean = true, 33 EnableStoreQueue: Boolean = true, 34 AddrBits: Int = 64, 35 VAddrBits: Int = 39, 36 PAddrBits: Int = 40, 37 HasFPU: Boolean = true, 38 FectchWidth: Int = 8, 39 EnableBPU: Boolean = true, 40 EnableBPD: Boolean = true, 41 EnableRAS: Boolean = true, 42 EnableLB: Boolean = false, 43 EnableLoop: Boolean = true, 44 EnableSC: Boolean = false, 45 HistoryLength: Int = 64, 46 BtbSize: Int = 2048, 47 JbtacSize: Int = 1024, 48 JbtacBanks: Int = 8, 49 RasSize: Int = 16, 50 CacheLineSize: Int = 512, 51 UBtbWays: Int = 16, 52 BtbWays: Int = 2, 53 54 EnableL1plusPrefetcher: Boolean = true, 55 IBufSize: Int = 32, 56 DecodeWidth: Int = 6, 57 RenameWidth: Int = 6, 58 CommitWidth: Int = 6, 59 BrqSize: Int = 32, 60 IssQueSize: Int = 12, 61 NRPhyRegs: Int = 160, 62 NRIntReadPorts: Int = 14, 63 NRIntWritePorts: Int = 8, 64 NRFpReadPorts: Int = 14, 65 NRFpWritePorts: Int = 8, 66 LoadQueueSize: Int = 64, 67 StoreQueueSize: Int = 48, 68 RoqSize: Int = 192, 69 dpParams: DispatchParameters = DispatchParameters( 70 IntDqSize = 32, 71 FpDqSize = 32, 72 LsDqSize = 32, 73 IntDqDeqWidth = 4, 74 FpDqDeqWidth = 4, 75 LsDqDeqWidth = 4 76 ), 77 exuParameters: ExuParameters = ExuParameters( 78 JmpCnt = 1, 79 AluCnt = 4, 80 MulCnt = 0, 81 MduCnt = 2, 82 FmacCnt = 4, 83 FmiscCnt = 2, 84 FmiscDivSqrtCnt = 0, 85 LduCnt = 2, 86 StuCnt = 2 87 ), 88 LoadPipelineWidth: Int = 2, 89 StorePipelineWidth: Int = 2, 90 StoreBufferSize: Int = 16, 91 RefillSize: Int = 512, 92 TlbEntrySize: Int = 32, 93 TlbSPEntrySize: Int = 4, 94 TlbL2EntrySize: Int = 256, // or 512 95 TlbL2SPEntrySize: Int = 16, 96 PtwL1EntrySize: Int = 16, 97 PtwL2EntrySize: Int = 256, 98 NumPerfCounters: Int = 16, 99 NrExtIntr: Int = 1 100) 101 102trait HasXSParameter { 103 104 val core = Parameters.get.coreParameters 105 val env = Parameters.get.envParameters 106 107 val XLEN = 64 108 val minFLen = 32 109 val fLen = 64 110 def xLen = 64 111 val HasMExtension = core.HasMExtension 112 val HasCExtension = core.HasCExtension 113 val HasDiv = core.HasDiv 114 val HasIcache = core.HasICache 115 val HasDcache = core.HasDCache 116 val EnableStoreQueue = core.EnableStoreQueue 117 val AddrBits = core.AddrBits // AddrBits is used in some cases 118 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 119 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 120 val AddrBytes = AddrBits / 8 // unused 121 val DataBits = XLEN 122 val DataBytes = DataBits / 8 123 val HasFPU = core.HasFPU 124 val FetchWidth = core.FectchWidth 125 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 126 val EnableBPU = core.EnableBPU 127 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 128 val EnableRAS = core.EnableRAS 129 val EnableLB = core.EnableLB 130 val EnableLoop = core.EnableLoop 131 val EnableSC = core.EnableSC 132 val HistoryLength = core.HistoryLength 133 val BtbSize = core.BtbSize 134 // val BtbWays = 4 135 val BtbBanks = PredictWidth 136 // val BtbSets = BtbSize / BtbWays 137 val JbtacSize = core.JbtacSize 138 val JbtacBanks = core.JbtacBanks 139 val RasSize = core.RasSize 140 val CacheLineSize = core.CacheLineSize 141 val CacheLineHalfWord = CacheLineSize / 16 142 val ExtHistoryLength = HistoryLength + 64 143 val UBtbWays = core.UBtbWays 144 val BtbWays = core.BtbWays 145 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 146 val IBufSize = core.IBufSize 147 val DecodeWidth = core.DecodeWidth 148 val RenameWidth = core.RenameWidth 149 val CommitWidth = core.CommitWidth 150 val BrqSize = core.BrqSize 151 val IssQueSize = core.IssQueSize 152 val BrTagWidth = log2Up(BrqSize) 153 val NRPhyRegs = core.NRPhyRegs 154 val PhyRegIdxWidth = log2Up(NRPhyRegs) 155 val RoqSize = core.RoqSize 156 val LoadQueueSize = core.LoadQueueSize 157 val StoreQueueSize = core.StoreQueueSize 158 val dpParams = core.dpParams 159 val exuParameters = core.exuParameters 160 val NRIntReadPorts = core.NRIntReadPorts 161 val NRIntWritePorts = core.NRIntWritePorts 162 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 163 val NRFpReadPorts = core.NRFpReadPorts 164 val NRFpWritePorts = core.NRFpWritePorts 165 val LoadPipelineWidth = core.LoadPipelineWidth 166 val StorePipelineWidth = core.StorePipelineWidth 167 val StoreBufferSize = core.StoreBufferSize 168 val RefillSize = core.RefillSize 169 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 170 val TlbEntrySize = core.TlbEntrySize 171 val TlbSPEntrySize = core.TlbSPEntrySize 172 val TlbL2EntrySize = core.TlbL2EntrySize 173 val TlbL2SPEntrySize = core.TlbL2SPEntrySize 174 val PtwL1EntrySize = core.PtwL1EntrySize 175 val PtwL2EntrySize = core.PtwL2EntrySize 176 val NumPerfCounters = core.NumPerfCounters 177 val NrExtIntr = core.NrExtIntr 178 179 val icacheParameters = ICacheParameters( 180 tagECC = Some("parity"), 181 dataECC = Some("parity"), 182 nMissEntries = 2 183 ) 184 185 val l1plusCacheParameters = L1plusCacheParameters( 186 tagECC = Some("secded"), 187 dataECC = Some("secded"), 188 nMissEntries = 8 189 ) 190 191 val dcacheParameters = DCacheParameters( 192 tagECC = Some("secded"), 193 dataECC = Some("secded"), 194 nMissEntries = 16, 195 nLoadMissEntries = 8, 196 nStoreMissEntries = 8 197 ) 198 199 val LRSCCycles = 100 200 201 202 // cache hierarchy configurations 203 val l1BusDataWidth = 256 204 205 // L2 configurations 206 val L1BusWidth = 256 207 val L2Size = 512 * 1024 // 512KB 208 val L2BlockSize = 64 209 val L2NWays = 8 210 val L2NSets = L2Size / L2BlockSize / L2NWays 211 212 // L3 configurations 213 val L2BusWidth = 256 214 val L3Size = 4 * 1024 * 1024 // 4MB 215 val L3BlockSize = 64 216 val L3NBanks = 4 217 val L3NWays = 8 218 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 219 220 // on chip network configurations 221 val L3BusWidth = 256 222 223 // icache prefetcher 224 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 225 enable = true, 226 _type = "stream", 227 streamParams = StreamPrefetchParameters( 228 streamCnt = 2, 229 streamSize = 4, 230 ageWidth = 4, 231 blockBytes = l1plusCacheParameters.blockBytes, 232 reallocStreamOnMissInstantly = true, 233 cacheName = "icache" 234 ) 235 ) 236 237 // dcache prefetcher 238 val l2PrefetcherParameters = L2PrefetcherParameters( 239 enable = true, 240 _type = "bop",// "stream" or "bop" 241 streamParams = StreamPrefetchParameters( 242 streamCnt = 4, 243 streamSize = 4, 244 ageWidth = 4, 245 blockBytes = L2BlockSize, 246 reallocStreamOnMissInstantly = true, 247 cacheName = "dcache" 248 ), 249 bopParams = BOPParameters( 250 rrTableEntries = 256, 251 rrTagBits = 12, 252 scoreBits = 5, 253 roundMax = 50, 254 badScore = 1, 255 blockBytes = L2BlockSize, 256 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 257 ), 258 ) 259} 260 261trait HasXSLog { this: RawModule => 262 implicit val moduleName: String = this.name 263} 264 265abstract class XSModule extends MultiIOModule 266 with HasXSParameter 267 with HasExceptionNO 268 with HasXSLog 269 with HasFPUParameters 270{ 271 def io: Record 272} 273 274//remove this trait after impl module logic 275trait NeedImpl { this: RawModule => 276 override protected def IO[T <: Data](iodef: T): T = { 277 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 278 val io = chisel3.experimental.IO(iodef) 279 io <> DontCare 280 io 281 } 282} 283 284abstract class XSBundle extends Bundle 285 with HasXSParameter 286 287case class EnviromentParameters 288( 289 FPGAPlatform: Boolean = true, 290 EnableDebug: Boolean = false, 291 EnablePerfDebug: Boolean = false 292) 293 294// object AddressSpace extends HasXSParameter { 295// // (start, size) 296// // address out of MMIO will be considered as DRAM 297// def mmio = List( 298// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 299// (0x40000000L, 0x40000000L) // external devices 300// ) 301 302// def isMMIO(addr: UInt): Bool = mmio.map(range => { 303// require(isPow2(range._2)) 304// val bits = log2Up(range._2) 305// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 306// }).reduce(_ || _) 307// } 308 309 310 311class XSCore()(implicit p: config.Parameters) extends LazyModule 312 with HasXSParameter 313 with HasExeBlockHelper 314{ 315 316 // to fast wake up fp, mem rs 317 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 318 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 319 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 320 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 321 322 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 323 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 324 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 325 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 326 327 // outer facing nodes 328 val frontend = LazyModule(new Frontend()) 329 val l1pluscache = LazyModule(new L1plusCache()) 330 val ptw = LazyModule(new PTW()) 331 val l2Prefetcher = LazyModule(new L2Prefetcher()) 332 val memBlock = LazyModule(new MemBlock( 333 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 334 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 335 fastFpOut = Seq(), 336 slowFpOut = loadExuConfigs, 337 fastIntOut = Seq(), 338 slowIntOut = loadExuConfigs 339 )) 340 341 lazy val module = new XSCoreImp(this) 342} 343 344class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 345 with HasXSParameter 346 with HasExeBlockHelper 347{ 348 val io = IO(new Bundle { 349 val externalInterrupt = new ExternalInterruptIO 350 val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits)) 351 }) 352 353 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 354 AddressSpace.printMemmap() 355 356 // to fast wake up fp, mem rs 357 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 358 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 359 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 360 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 361 362 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 363 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 364 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 365 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 366 367 val ctrlBlock = Module(new CtrlBlock) 368 val integerBlock = Module(new IntegerBlock( 369 fastWakeUpIn = fpBlockFastWakeUpInt, 370 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 371 fastFpOut = intBlockFastWakeUpFp, 372 slowFpOut = intBlockSlowWakeUpFp, 373 fastIntOut = intBlockFastWakeUpInt, 374 slowIntOut = intBlockSlowWakeUpInt 375 )) 376 val floatBlock = Module(new FloatBlock( 377 fastWakeUpIn = intBlockFastWakeUpFp, 378 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 379 fastFpOut = fpBlockFastWakeUpFp, 380 slowFpOut = fpBlockSlowWakeUpFp, 381 fastIntOut = fpBlockFastWakeUpInt, 382 slowIntOut = fpBlockSlowWakeUpInt 383 )) 384 385 val frontend = outer.frontend.module 386 val memBlock = outer.memBlock.module 387 val l1pluscache = outer.l1pluscache.module 388 val ptw = outer.ptw.module 389 val l2Prefetcher = outer.l2Prefetcher.module 390 391 frontend.io.backend <> ctrlBlock.io.frontend 392 frontend.io.sfence <> integerBlock.io.fenceio.sfence 393 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 394 395 frontend.io.icacheMemAcq <> l1pluscache.io.req 396 l1pluscache.io.resp <> frontend.io.icacheMemGrant 397 l1pluscache.io.flush := frontend.io.l1plusFlush 398 frontend.io.fencei := integerBlock.io.fenceio.fencei 399 400 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 401 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 402 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 403 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 404 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 405 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 406 407 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 408 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 409 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 410 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 411 412 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 413 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 414 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 415 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 416 417 418 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 419 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 420 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 421 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 422 423 val wakeUpMem = Seq( 424 integerBlock.io.wakeUpIntOut, 425 integerBlock.io.wakeUpFpOut, 426 floatBlock.io.wakeUpIntOut, 427 floatBlock.io.wakeUpFpOut 428 ) 429 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 430 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 431 val raw = WireInit(f) 432 raw 433 })) 434 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 435 val raw = WireInit(s) 436 raw 437 })) 438 439 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 440 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 441 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 442 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 443 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 444 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 445 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 446 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 447 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 448 integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo 449 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 450 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 451 452 floatBlock.io.frm <> integerBlock.io.csrio.frm 453 454 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 455 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 456 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 457 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 458 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 459 460 ptw.io.tlb(0) <> memBlock.io.ptw 461 ptw.io.tlb(1) <> frontend.io.ptw 462 ptw.io.sfence <> integerBlock.io.fenceio.sfence 463 ptw.io.csr <> integerBlock.io.csrio.tlb 464 465 val l2PrefetcherIn = Wire(Decoupled(new MissReq)) 466 if (l2PrefetcherParameters.enable && l2PrefetcherParameters._type == "bop") { 467 l2PrefetcherIn.valid := io.l2ToPrefetcher.acquire.valid 468 l2PrefetcherIn.bits := DontCare 469 l2PrefetcherIn.bits.addr := io.l2ToPrefetcher.acquire.bits.address 470 l2PrefetcherIn.bits.cmd := Mux(io.l2ToPrefetcher.acquire.bits.write, MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD) 471 } else { 472 l2PrefetcherIn <> memBlock.io.toDCachePrefetch 473 } 474 l2Prefetcher.io.in <> l2PrefetcherIn 475 476 if (!env.FPGAPlatform) { 477 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 478 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 479 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 480 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 481 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 482 } 483 484} 485