1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 16import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 17import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 20import freechips.rocketchip.tile.HasFPUParameters 21import utils._ 22 23case class XSCoreParameters 24( 25 XLEN: Int = 64, 26 HasMExtension: Boolean = true, 27 HasCExtension: Boolean = true, 28 HasDiv: Boolean = true, 29 HasICache: Boolean = true, 30 HasDCache: Boolean = true, 31 EnableStoreQueue: Boolean = true, 32 AddrBits: Int = 64, 33 VAddrBits: Int = 39, 34 PAddrBits: Int = 40, 35 HasFPU: Boolean = true, 36 FectchWidth: Int = 8, 37 EnableBPU: Boolean = true, 38 EnableBPD: Boolean = true, 39 EnableRAS: Boolean = true, 40 EnableLB: Boolean = false, 41 EnableLoop: Boolean = false, 42 EnableSC: Boolean = false, 43 HistoryLength: Int = 64, 44 BtbSize: Int = 2048, 45 JbtacSize: Int = 1024, 46 JbtacBanks: Int = 8, 47 RasSize: Int = 16, 48 CacheLineSize: Int = 512, 49 UBtbWays: Int = 16, 50 BtbWays: Int = 2, 51 IBufSize: Int = 64, 52 DecodeWidth: Int = 6, 53 RenameWidth: Int = 6, 54 CommitWidth: Int = 6, 55 BrqSize: Int = 32, 56 IssQueSize: Int = 12, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 IntDqSize = 32, 67 FpDqSize = 32, 68 LsDqSize = 32, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4 72 ), 73 exuParameters: ExuParameters = ExuParameters( 74 JmpCnt = 1, 75 AluCnt = 4, 76 MulCnt = 0, 77 MduCnt = 2, 78 FmacCnt = 4, 79 FmiscCnt = 2, 80 FmiscDivSqrtCnt = 0, 81 LduCnt = 2, 82 StuCnt = 2 83 ), 84 LoadPipelineWidth: Int = 2, 85 StorePipelineWidth: Int = 2, 86 StoreBufferSize: Int = 16, 87 RefillSize: Int = 512, 88 TlbEntrySize: Int = 32, 89 TlbL2EntrySize: Int = 256, // or 512 90 PtwL1EntrySize: Int = 16, 91 PtwL2EntrySize: Int = 256, 92 NumPerfCounters: Int = 16 93) 94 95trait HasXSParameter { 96 97 val core = Parameters.get.coreParameters 98 val env = Parameters.get.envParameters 99 100 val XLEN = 64 101 val minFLen = 32 102 val fLen = 64 103 def xLen = 64 104 val HasMExtension = core.HasMExtension 105 val HasCExtension = core.HasCExtension 106 val HasDiv = core.HasDiv 107 val HasIcache = core.HasICache 108 val HasDcache = core.HasDCache 109 val EnableStoreQueue = core.EnableStoreQueue 110 val AddrBits = core.AddrBits // AddrBits is used in some cases 111 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 112 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 113 val AddrBytes = AddrBits / 8 // unused 114 val DataBits = XLEN 115 val DataBytes = DataBits / 8 116 val HasFPU = core.HasFPU 117 val FetchWidth = core.FectchWidth 118 val PredictWidth = FetchWidth * 2 119 val EnableBPU = core.EnableBPU 120 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 121 val EnableRAS = core.EnableRAS 122 val EnableLB = core.EnableLB 123 val EnableLoop = core.EnableLoop 124 val EnableSC = core.EnableSC 125 val HistoryLength = core.HistoryLength 126 val BtbSize = core.BtbSize 127 // val BtbWays = 4 128 val BtbBanks = PredictWidth 129 // val BtbSets = BtbSize / BtbWays 130 val JbtacSize = core.JbtacSize 131 val JbtacBanks = core.JbtacBanks 132 val RasSize = core.RasSize 133 val CacheLineSize = core.CacheLineSize 134 val CacheLineHalfWord = CacheLineSize / 16 135 val ExtHistoryLength = HistoryLength + 64 136 val UBtbWays = core.UBtbWays 137 val BtbWays = core.BtbWays 138 val IBufSize = core.IBufSize 139 val DecodeWidth = core.DecodeWidth 140 val RenameWidth = core.RenameWidth 141 val CommitWidth = core.CommitWidth 142 val BrqSize = core.BrqSize 143 val IssQueSize = core.IssQueSize 144 val BrTagWidth = log2Up(BrqSize) 145 val NRPhyRegs = core.NRPhyRegs 146 val PhyRegIdxWidth = log2Up(NRPhyRegs) 147 val RoqSize = core.RoqSize 148 val LoadQueueSize = core.LoadQueueSize 149 val StoreQueueSize = core.StoreQueueSize 150 val dpParams = core.dpParams 151 val exuParameters = core.exuParameters 152 val NRIntReadPorts = core.NRIntReadPorts 153 val NRIntWritePorts = core.NRIntWritePorts 154 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 155 val NRFpReadPorts = core.NRFpReadPorts 156 val NRFpWritePorts = core.NRFpWritePorts 157 val LoadPipelineWidth = core.LoadPipelineWidth 158 val StorePipelineWidth = core.StorePipelineWidth 159 val StoreBufferSize = core.StoreBufferSize 160 val RefillSize = core.RefillSize 161 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 162 val TlbEntrySize = core.TlbEntrySize 163 val TlbL2EntrySize = core.TlbL2EntrySize 164 val PtwL1EntrySize = core.PtwL1EntrySize 165 val PtwL2EntrySize = core.PtwL2EntrySize 166 val NumPerfCounters = core.NumPerfCounters 167 168 val icacheParameters = ICacheParameters( 169 tagECC = Some("secded"), 170 dataECC = Some("secded"), 171 nMissEntries = 2 172 ) 173 174 val l1plusCacheParameters = L1plusCacheParameters( 175 tagECC = Some("secded"), 176 dataECC = Some("secded"), 177 nMissEntries = 8 178 ) 179 180 val dcacheParameters = DCacheParameters( 181 tagECC = Some("secded"), 182 dataECC = Some("secded"), 183 nMissEntries = 16, 184 nLoadMissEntries = 8, 185 nStoreMissEntries = 8 186 ) 187 188 val LRSCCycles = 100 189 190 191 // cache hierarchy configurations 192 val l1BusDataWidth = 256 193 194 // L2 configurations 195 val L1BusWidth = 256 196 val L2Size = 512 * 1024 // 512KB 197 val L2BlockSize = 64 198 val L2NWays = 8 199 val L2NSets = L2Size / L2BlockSize / L2NWays 200 201 // L3 configurations 202 val L2BusWidth = 256 203 val L3Size = 4 * 1024 * 1024 // 4MB 204 val L3BlockSize = 64 205 val L3NBanks = 4 206 val L3NWays = 8 207 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 208 209 // on chip network configurations 210 val L3BusWidth = 256 211} 212 213trait HasXSLog { this: RawModule => 214 implicit val moduleName: String = this.name 215} 216 217abstract class XSModule extends MultiIOModule 218 with HasXSParameter 219 with HasExceptionNO 220 with HasXSLog 221 with HasFPUParameters 222{ 223 def io: Record 224} 225 226//remove this trait after impl module logic 227trait NeedImpl { this: RawModule => 228 override protected def IO[T <: Data](iodef: T): T = { 229 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 230 val io = chisel3.experimental.IO(iodef) 231 io <> DontCare 232 io 233 } 234} 235 236abstract class XSBundle extends Bundle 237 with HasXSParameter 238 239case class EnviromentParameters 240( 241 FPGAPlatform: Boolean = true, 242 EnableDebug: Boolean = false 243) 244 245object AddressSpace extends HasXSParameter { 246 // (start, size) 247 // address out of MMIO will be considered as DRAM 248 def mmio = List( 249 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 250 (0x40000000L, 0x40000000L) // external devices 251 ) 252 253 def isMMIO(addr: UInt): Bool = mmio.map(range => { 254 require(isPow2(range._2)) 255 val bits = log2Up(range._2) 256 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 257 }).reduce(_ || _) 258} 259 260 261 262class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 263 264 // outer facing nodes 265 val dcache = LazyModule(new DCache()) 266 val uncache = LazyModule(new Uncache()) 267 val l1pluscache = LazyModule(new L1plusCache()) 268 val ptw = LazyModule(new PTW()) 269 270 lazy val module = new XSCoreImp(this) 271} 272 273class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 274 with HasXSParameter 275 with HasExeBlockHelper 276{ 277 val io = IO(new Bundle { 278 val externalInterrupt = new ExternalInterruptIO 279 }) 280 281 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 282 283 // to fast wake up fp, mem rs 284 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 285 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 286 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 287 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 288 289 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 290 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 291 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 292 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 293 294 val frontend = Module(new Frontend) 295 val ctrlBlock = Module(new CtrlBlock) 296 val integerBlock = Module(new IntegerBlock( 297 fastWakeUpIn = fpBlockFastWakeUpInt, 298 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 299 fastFpOut = intBlockFastWakeUpFp, 300 slowFpOut = intBlockSlowWakeUpFp, 301 fastIntOut = intBlockFastWakeUpInt, 302 slowIntOut = intBlockSlowWakeUpInt 303 )) 304 val floatBlock = Module(new FloatBlock( 305 fastWakeUpIn = intBlockFastWakeUpFp, 306 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 307 fastFpOut = fpBlockFastWakeUpFp, 308 slowFpOut = fpBlockSlowWakeUpFp, 309 fastIntOut = fpBlockFastWakeUpInt, 310 slowIntOut = fpBlockSlowWakeUpInt 311 )) 312 val memBlock = Module(new MemBlock( 313 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 314 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 315 fastFpOut = Seq(), 316 slowFpOut = loadExuConfigs, 317 fastIntOut = Seq(), 318 slowIntOut = loadExuConfigs 319 )) 320 321 val dcache = outer.dcache.module 322 val uncache = outer.uncache.module 323 val l1pluscache = outer.l1pluscache.module 324 val ptw = outer.ptw.module 325 326 327 frontend.io.backend <> ctrlBlock.io.frontend 328 frontend.io.sfence <> integerBlock.io.fenceio.sfence 329 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 330 331 frontend.io.icacheMemAcq <> l1pluscache.io.req 332 l1pluscache.io.resp <> frontend.io.icacheMemGrant 333 l1pluscache.io.flush := frontend.io.l1plusFlush 334 frontend.io.fencei := integerBlock.io.fenceio.fencei 335 336 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 337 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 338 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 339 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 340 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 341 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 342 343 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 344 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 345 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 346 347 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 348 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 349 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 350 351 352 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 353 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 354 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 355 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 356 357 val wakeUpMem = Seq( 358 integerBlock.io.wakeUpIntOut, 359 integerBlock.io.wakeUpFpOut, 360 floatBlock.io.wakeUpIntOut, 361 floatBlock.io.wakeUpFpOut 362 ) 363 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 364 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 365 val raw = WireInit(f) 366 raw 367 })) 368 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 369 val raw = WireInit(s) 370 raw 371 })) 372 373 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 374 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 375 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 376 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 377 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 378 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 379 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 380 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 381 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 382 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 383 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 384 385 floatBlock.io.frm <> integerBlock.io.csrio.frm 386 387 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 388 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 389 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 390 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 391 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 392 393 ptw.io.tlb(0) <> memBlock.io.ptw 394 ptw.io.tlb(1) <> frontend.io.ptw 395 ptw.io.sfence <> integerBlock.io.fenceio.sfence 396 ptw.io.csr <> integerBlock.io.csrio.tlb 397 398 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 399 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 400 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 401 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 402 uncache.io.lsq <> memBlock.io.dcache.uncache 403 404 if (!env.FPGAPlatform) { 405 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 406 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 407 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 408 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 409 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 410 } 411 412} 413