1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.backend._ 6import xiangshan.backend.fu.HasExceptionNO 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.frontend._ 9import xiangshan.mem._ 10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheWrapper, L1plusCacheParameters, PTWWrapper, PTWRepeater, PTWFilter} 11import xiangshan.cache.prefetch._ 12import chipsalliance.rocketchip.config 13import chipsalliance.rocketchip.config.Parameters 14import freechips.rocketchip.diplomacy.{Description, LazyModule, LazyModuleImp, ResourceAnchors, ResourceBindings, SimpleDevice} 15import freechips.rocketchip.tile.HasFPUParameters 16import system.{HasSoCParameter, L1CacheErrorInfo} 17import utils._ 18 19object hartIdCore extends (() => Int) { 20 var x = 0 21 22 def apply(): Int = { 23 x = x + 1 24 x - 1 25 } 26} 27 28abstract class XSModule(implicit val p: Parameters) extends MultiIOModule 29 with HasXSParameter 30 with HasExceptionNO 31 with HasFPUParameters { 32 def io: Record 33} 34 35//remove this trait after impl module logic 36trait NeedImpl { 37 this: RawModule => 38 override protected def IO[T <: Data](iodef: T): T = { 39 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 40 val io = chisel3.experimental.IO(iodef) 41 io <> DontCare 42 io 43 } 44} 45 46abstract class XSBundle(implicit val p: Parameters) extends Bundle 47 with HasXSParameter 48 49case class EnviromentParameters 50( 51 FPGAPlatform: Boolean = true, 52 EnableDebug: Boolean = false, 53 EnablePerfDebug: Boolean = true, 54 DualCore: Boolean = false 55) 56 57abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 58 with HasXSParameter 59{ 60 // outer facing nodes 61 val frontend = LazyModule(new Frontend()) 62 val l1pluscache = LazyModule(new L1plusCacheWrapper()) 63 val ptw = LazyModule(new PTWWrapper()) 64 val memBlock = LazyModule(new MemBlock( 65 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 66 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 67 fastWakeUpOut = Seq(), 68 slowWakeUpOut = loadExuConfigs, 69 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 70 )) 71 72} 73 74class XSCore()(implicit p: config.Parameters) extends XSCoreBase 75 with HasXSDts 76{ 77 lazy val module = new XSCoreImp(this) 78} 79 80class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 81 with HasXSParameter 82 with HasSoCParameter 83 with HasExeBlockHelper { 84 val io = IO(new Bundle { 85 val hartId = Input(UInt(64.W)) 86 val externalInterrupt = new ExternalInterruptIO 87 val l2_pf_enable = Output(Bool()) 88 val l1plus_error, icache_error, dcache_error = Output(new L1CacheErrorInfo) 89 }) 90 91 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 92 AddressSpace.checkMemmap() 93 AddressSpace.printMemmap() 94 95 // to fast wake up fp, mem rs 96 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 97 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 98 99 val ctrlBlock = Module(new CtrlBlock) 100 val integerBlock = Module(new IntegerBlock( 101 fastWakeUpIn = Seq(), 102 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 103 memFastWakeUpIn = loadExuConfigs, 104 fastWakeUpOut = intBlockFastWakeUp, 105 slowWakeUpOut = intBlockSlowWakeUp 106 )) 107 val floatBlock = Module(new FloatBlock( 108 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 109 memSlowWakeUpIn = loadExuConfigs, 110 fastWakeUpOut = Seq(), 111 slowWakeUpOut = fpExuConfigs 112 )) 113 114 val frontend = outer.frontend.module 115 val memBlock = outer.memBlock.module 116 val l1pluscache = outer.l1pluscache.module 117 val ptw = outer.ptw.module 118 119 io.l1plus_error <> l1pluscache.io.error 120 io.icache_error <> frontend.io.error 121 io.dcache_error <> memBlock.io.error 122 123 frontend.io.backend <> ctrlBlock.io.frontend 124 frontend.io.sfence <> integerBlock.io.fenceio.sfence 125 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 126 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 127 128 frontend.io.icacheMemAcq <> l1pluscache.io.req 129 l1pluscache.io.resp <> frontend.io.icacheMemGrant 130 l1pluscache.io.flush := frontend.io.l1plusFlush 131 frontend.io.fencei := integerBlock.io.fenceio.fencei 132 133 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 134 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 135 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 136 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 137 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 138 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 139 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 140 141 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 142 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 143 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 144 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 145 146 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 147 val fpBlockWakeUpInt = fpExuConfigs 148 .zip(floatBlock.io.wakeUpOut.slow) 149 .filter(_._1.writeIntRf) 150 .map(_._2) 151 152 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 153 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 154 .zip(integerBlock.io.wakeUpOut.slow) 155 .filter(_._1.writeFpRf) 156 .map(_._2) 157 158 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 159 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 160 integerBlock.io.memFastWakeUp <> memBlock.io.ldFastWakeUpInt 161 162 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 163 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 164 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 165 166 val wakeUpMem = Seq( 167 integerBlock.io.wakeUpOut, 168 floatBlock.io.wakeUpOut, 169 ) 170 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 171 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 172 // Note: 'WireInit' is used to block 'ready's from memBlock, 173 // we don't need 'ready's from memBlock 174 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 175 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 176 memBlock.io.intWbOut := integerBlock.io.intWbOut 177 memBlock.io.fpWbOut := floatBlock.io.fpWbOut 178 179 integerBlock.io.csrio.hartId <> io.hartId 180 integerBlock.io.csrio.perf <> DontCare 181 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 182 integerBlock.io.csrio.perf.bpuInfo <> ctrlBlock.io.perfInfo.bpuInfo 183 integerBlock.io.csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 184 integerBlock.io.csrio.perf.memInfo <> memBlock.io.memInfo 185 integerBlock.io.csrio.perf.frontendInfo <> frontend.io.frontendInfo 186 187 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 188 integerBlock.io.csrio.fpu.isIllegal := false.B 189 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 190 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 191 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 192 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 193 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 194 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 195 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 196 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 197 198 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 199 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 200 201 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 202 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 203 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 204 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 205 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 206 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 207 208 val itlbRepeater = Module(new PTWRepeater()) 209 val dtlbRepeater = Module(new PTWFilter(LoadPipelineWidth + StorePipelineWidth, PtwMissQueueSize)) 210 itlbRepeater.io.tlb <> frontend.io.ptw 211 dtlbRepeater.io.tlb <> memBlock.io.ptw 212 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 213 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 214 ptw.io.tlb(0) <> itlbRepeater.io.ptw 215 ptw.io.tlb(1) <> dtlbRepeater.io.ptw 216 ptw.io.sfence <> integerBlock.io.fenceio.sfence 217 ptw.io.csr <> integerBlock.io.csrio.tlb 218 219 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 220 assert(l2PrefetcherParameters._type == "bop") 221 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 222 223 val l1plus_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform)) 224 l1pluscache.reset := l1plus_reset_gen.io.out 225 226 val ptw_reset_gen = Module(new ResetGen(2, !debugOpts.FPGAPlatform)) 227 ptw.reset := ptw_reset_gen.io.out 228 itlbRepeater.reset := ptw_reset_gen.io.out 229 dtlbRepeater.reset := ptw_reset_gen.io.out 230 231 val memBlock_reset_gen = Module(new ResetGen(3, !debugOpts.FPGAPlatform)) 232 memBlock.reset := memBlock_reset_gen.io.out 233 234 val intBlock_reset_gen = Module(new ResetGen(4, !debugOpts.FPGAPlatform)) 235 integerBlock.reset := intBlock_reset_gen.io.out 236 237 val fpBlock_reset_gen = Module(new ResetGen(5, !debugOpts.FPGAPlatform)) 238 floatBlock.reset := fpBlock_reset_gen.io.out 239 240 val ctrlBlock_reset_gen = Module(new ResetGen(6, !debugOpts.FPGAPlatform)) 241 ctrlBlock.reset := ctrlBlock_reset_gen.io.out 242 243 val frontend_reset_gen = Module(new ResetGen(7, !debugOpts.FPGAPlatform)) 244 frontend.reset := frontend_reset_gen.io.out 245} 246