1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import device.MsiInfoBundle 24import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.backend.fu.PMPRespBundle 31import xiangshan.cache.mmu._ 32import xiangshan.frontend._ 33import xiangshan.mem.L1PrefetchFuzzer 34import scala.collection.mutable.ListBuffer 35import xiangshan.cache.mmu.TlbRequestIO 36 37abstract class XSModule(implicit val p: Parameters) extends Module 38 with HasXSParameter 39 with HasFPUParameters 40 41//remove this trait after impl module logic 42trait NeedImpl { 43 this: RawModule => 44 protected def IO[T <: Data](iodef: T): T = { 45 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 46 val io = chisel3.IO(iodef) 47 io <> DontCare 48 io 49 } 50} 51 52abstract class XSBundle(implicit val p: Parameters) extends Bundle 53 with HasXSParameter 54 55abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 56 with HasXSParameter 57{ 58 override def shouldBeInlined: Boolean = false 59 // outer facing nodes 60 val frontend = LazyModule(new Frontend()) 61 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 62 val backend = LazyModule(new Backend(backendParams)) 63 64 val memBlock = LazyModule(new MemBlock) 65 66 memBlock.frontendBridge.icache_node := frontend.icache.clientNode 67 memBlock.frontendBridge.instr_uncache_node := frontend.instrUncache.clientNode 68} 69 70class XSCore()(implicit p: config.Parameters) extends XSCoreBase 71 with HasXSDts 72{ 73 lazy val module = new XSCoreImp(this) 74} 75 76class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 77 with HasXSParameter 78 with HasSoCParameter { 79 val io = IO(new Bundle { 80 val hartId = Input(UInt(hartIdLen.W)) 81 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 82 val clintTime = Input(ValidIO(UInt(64.W))) 83 val reset_vector = Input(UInt(PAddrBits.W)) 84 val cpu_halt = Output(Bool()) 85 val resetIsInFrontend = Output(Bool()) 86 val l2_pf_enable = Output(Bool()) 87 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 88 val beu_errors = Output(new XSL1BusErrors()) 89 val l2_hint = Input(Valid(new L2ToL1Hint())) 90 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 91 val l2_pmp_resp = new PMPRespBundle 92 val l2PfqBusy = Input(Bool()) 93 val debugTopDown = new Bundle { 94 val robTrueCommit = Output(UInt(64.W)) 95 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 96 val l2MissMatch = Input(Bool()) 97 val l3MissMatch = Input(Bool()) 98 } 99 }) 100 101 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 102 103 val frontend = outer.frontend.module 104 val backend = outer.backend.module 105 val memBlock = outer.memBlock.module 106 107 frontend.io.hartId := memBlock.io.inner_hartId 108 frontend.io.reset_vector := memBlock.io.inner_reset_vector 109 frontend.io.softPrefetch <> memBlock.io.ifetchPrefetch 110 frontend.io.backend <> backend.io.frontend 111 frontend.io.sfence <> backend.io.frontendSfence 112 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 113 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 114 frontend.io.fencei <> backend.io.fenceio.fencei 115 116 backend.io.fromTop := memBlock.io.mem_to_ooo.topToBackendBypass 117 118 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 119 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 120 sink.valid := source.valid 121 sink.bits := 0.U.asTypeOf(sink.bits) 122 sink.bits.robIdx := source.bits.uop.robIdx 123 sink.bits.ssid := source.bits.uop.ssid 124 sink.bits.storeSetHit := source.bits.uop.storeSetHit 125 // The other signals have not been used 126 } 127 backend.io.mem.memoryViolation := memBlock.io.mem_to_ooo.memoryViolation 128 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 129 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 130 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 131 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 132 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 133 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 134 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 135 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 136 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 137 backend.io.mem.ldaIqFeedback := memBlock.io.mem_to_ooo.ldaIqFeedback 138 backend.io.mem.staIqFeedback := memBlock.io.mem_to_ooo.staIqFeedback 139 backend.io.mem.hyuIqFeedback := memBlock.io.mem_to_ooo.hyuIqFeedback 140 backend.io.mem.vstuIqFeedback := memBlock.io.mem_to_ooo.vstuIqFeedback 141 backend.io.mem.vlduIqFeedback := memBlock.io.mem_to_ooo.vlduIqFeedback 142 backend.io.mem.ldCancel := memBlock.io.mem_to_ooo.ldCancel 143 backend.io.mem.wakeup := memBlock.io.mem_to_ooo.wakeup 144 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 145 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 146 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 147 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 148 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 149 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 150 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 151 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 152 153 // memblock error exception writeback, 1 cycle after normal writeback 154 backend.io.mem.s3_delayed_load_error := memBlock.io.mem_to_ooo.s3_delayed_load_error 155 156 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 157 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 158 backend.io.mem.debugLS := memBlock.io.debug_ls 159 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 160 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 161 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 162 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 163 164 backend.io.perf.frontendInfo := frontend.io.frontendInfo 165 backend.io.perf.memInfo := memBlock.io.memInfo 166 backend.io.perf.perfEventsFrontend := frontend.getPerf 167 backend.io.perf.perfEventsLsu := memBlock.getPerf 168 backend.io.perf.perfEventsHc := io.perfEvents 169 backend.io.perf.perfEventsBackend := DontCare 170 backend.io.perf.retiredInstr := DontCare 171 backend.io.perf.ctrlInfo := DontCare 172 173 // top -> memBlock 174 memBlock.io.fromTopToBackend.clintTime := io.clintTime 175 memBlock.io.fromTopToBackend.msiInfo := io.msiInfo 176 memBlock.io.hartId := io.hartId 177 memBlock.io.outer_reset_vector := io.reset_vector 178 // frontend -> memBlock 179 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 180 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 181 memBlock.io.ooo_to_mem.backendToTopBypass := backend.io.toTop 182 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 183 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 184 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 185 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 186 backend.io.mem.issueHysta.foreach(_.ready := false.B) // this fake port should not be used 187 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 188 189 // By default, instructions do not have exceptions when they enter the function units. 190 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 191 memBlock.io.ooo_to_mem.loadPc := backend.io.mem.loadPcRead 192 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 193 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 194 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 195 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 196 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 197 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 198 199 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 200 201 memBlock.io.redirect := backend.io.mem.redirect 202 memBlock.io.ooo_to_mem.csrCtrl := backend.io.mem.csrCtrl 203 memBlock.io.ooo_to_mem.tlbCsr := backend.io.mem.tlbCsr 204 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 205 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 206 memBlock.io.ooo_to_mem.lsqio.pendingUncacheld := backend.io.mem.robLsqIO.pendingUncacheld 207 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 208 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 209 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 210 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 211 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 212 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 213 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 214 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 215 216 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 217 memBlock.io.l2_hint.valid := io.l2_hint.valid 218 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 219 memBlock.io.l2_tlb_req <> io.l2_tlb_req 220 memBlock.io.l2_pmp_resp <> io.l2_pmp_resp 221 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 222 memBlock.io.l2PfqBusy := io.l2PfqBusy 223 224 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 225 226 // top-down info 227 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 228 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 229 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 230 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 231 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 232 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 233 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 234 memBlock.io.debugRolling := backend.io.debugRolling 235 236 io.cpu_halt := memBlock.io.outer_cpu_halt 237 io.resetIsInFrontend := frontend.reset.asBool 238 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 239 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 240 io.beu_errors.l2 <> DontCare 241 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 242 243 if (debugOpts.ResetGen) { 244 backend.reset := memBlock.reset_backend 245 frontend.reset := backend.io.frontendReset 246 } 247} 248