1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 16import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 17import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 20import freechips.rocketchip.tile.HasFPUParameters 21import utils._ 22 23case class XSCoreParameters 24( 25 XLEN: Int = 64, 26 HasMExtension: Boolean = true, 27 HasCExtension: Boolean = true, 28 HasDiv: Boolean = true, 29 HasICache: Boolean = true, 30 HasDCache: Boolean = true, 31 EnableStoreQueue: Boolean = true, 32 AddrBits: Int = 64, 33 VAddrBits: Int = 39, 34 PAddrBits: Int = 40, 35 HasFPU: Boolean = true, 36 FectchWidth: Int = 8, 37 EnableBPU: Boolean = true, 38 EnableBPD: Boolean = true, 39 EnableRAS: Boolean = true, 40 EnableLB: Boolean = false, 41 EnableLoop: Boolean = false, 42 EnableSC: Boolean = false, 43 HistoryLength: Int = 64, 44 BtbSize: Int = 2048, 45 JbtacSize: Int = 1024, 46 JbtacBanks: Int = 8, 47 RasSize: Int = 16, 48 CacheLineSize: Int = 512, 49 UBtbWays: Int = 16, 50 BtbWays: Int = 2, 51 IBufSize: Int = 64, 52 DecodeWidth: Int = 6, 53 RenameWidth: Int = 6, 54 CommitWidth: Int = 6, 55 BrqSize: Int = 32, 56 IssQueSize: Int = 12, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 DqEnqWidth = 4, 67 IntDqSize = 24, 68 FpDqSize = 24, 69 LsDqSize = 24, 70 IntDqDeqWidth = 4, 71 FpDqDeqWidth = 4, 72 LsDqDeqWidth = 4 73 ), 74 exuParameters: ExuParameters = ExuParameters( 75 JmpCnt = 1, 76 AluCnt = 4, 77 MulCnt = 0, 78 MduCnt = 2, 79 FmacCnt = 4, 80 FmiscCnt = 2, 81 FmiscDivSqrtCnt = 0, 82 LduCnt = 2, 83 StuCnt = 2 84 ), 85 LoadPipelineWidth: Int = 2, 86 StorePipelineWidth: Int = 2, 87 StoreBufferSize: Int = 16, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbL2EntrySize: Int = 256, // or 512 91 PtwL1EntrySize: Int = 16, 92 PtwL2EntrySize: Int = 256, 93 NumPerfCounters: Int = 16 94) 95 96trait HasXSParameter { 97 98 val core = Parameters.get.coreParameters 99 val env = Parameters.get.envParameters 100 101 val XLEN = 64 102 val minFLen = 32 103 val fLen = 64 104 def xLen = 64 105 val HasMExtension = core.HasMExtension 106 val HasCExtension = core.HasCExtension 107 val HasDiv = core.HasDiv 108 val HasIcache = core.HasICache 109 val HasDcache = core.HasDCache 110 val EnableStoreQueue = core.EnableStoreQueue 111 val AddrBits = core.AddrBits // AddrBits is used in some cases 112 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 113 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 114 val AddrBytes = AddrBits / 8 // unused 115 val DataBits = XLEN 116 val DataBytes = DataBits / 8 117 val HasFPU = core.HasFPU 118 val FetchWidth = core.FectchWidth 119 val PredictWidth = FetchWidth * 2 120 val EnableBPU = core.EnableBPU 121 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 122 val EnableRAS = core.EnableRAS 123 val EnableLB = core.EnableLB 124 val EnableLoop = core.EnableLoop 125 val EnableSC = core.EnableSC 126 val HistoryLength = core.HistoryLength 127 val BtbSize = core.BtbSize 128 // val BtbWays = 4 129 val BtbBanks = PredictWidth 130 // val BtbSets = BtbSize / BtbWays 131 val JbtacSize = core.JbtacSize 132 val JbtacBanks = core.JbtacBanks 133 val RasSize = core.RasSize 134 val CacheLineSize = core.CacheLineSize 135 val CacheLineHalfWord = CacheLineSize / 16 136 val ExtHistoryLength = HistoryLength + 64 137 val UBtbWays = core.UBtbWays 138 val BtbWays = core.BtbWays 139 val IBufSize = core.IBufSize 140 val DecodeWidth = core.DecodeWidth 141 val RenameWidth = core.RenameWidth 142 val CommitWidth = core.CommitWidth 143 val BrqSize = core.BrqSize 144 val IssQueSize = core.IssQueSize 145 val BrTagWidth = log2Up(BrqSize) 146 val NRPhyRegs = core.NRPhyRegs 147 val PhyRegIdxWidth = log2Up(NRPhyRegs) 148 val RoqSize = core.RoqSize 149 val LoadQueueSize = core.LoadQueueSize 150 val StoreQueueSize = core.StoreQueueSize 151 val dpParams = core.dpParams 152 val exuParameters = core.exuParameters 153 val NRIntReadPorts = core.NRIntReadPorts 154 val NRIntWritePorts = core.NRIntWritePorts 155 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 156 val NRFpReadPorts = core.NRFpReadPorts 157 val NRFpWritePorts = core.NRFpWritePorts 158 val LoadPipelineWidth = core.LoadPipelineWidth 159 val StorePipelineWidth = core.StorePipelineWidth 160 val StoreBufferSize = core.StoreBufferSize 161 val RefillSize = core.RefillSize 162 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 163 val TlbEntrySize = core.TlbEntrySize 164 val TlbL2EntrySize = core.TlbL2EntrySize 165 val PtwL1EntrySize = core.PtwL1EntrySize 166 val PtwL2EntrySize = core.PtwL2EntrySize 167 val NumPerfCounters = core.NumPerfCounters 168 169 val icacheParameters = ICacheParameters( 170 nMissEntries = 2 171 ) 172 173 val l1plusCacheParameters = L1plusCacheParameters( 174 tagECC = Some("secded"), 175 dataECC = Some("secded"), 176 nMissEntries = 8 177 ) 178 179 val dcacheParameters = DCacheParameters( 180 tagECC = Some("secded"), 181 dataECC = Some("secded"), 182 nMissEntries = 16, 183 nLoadMissEntries = 8, 184 nStoreMissEntries = 8 185 ) 186 187 val LRSCCycles = 100 188 189 190 // cache hierarchy configurations 191 val l1BusDataWidth = 256 192 193 // L2 configurations 194 val L1BusWidth = 256 195 val L2Size = 512 * 1024 // 512KB 196 val L2BlockSize = 64 197 val L2NWays = 8 198 val L2NSets = L2Size / L2BlockSize / L2NWays 199 200 // L3 configurations 201 val L2BusWidth = 256 202 val L3Size = 4 * 1024 * 1024 // 4MB 203 val L3BlockSize = 64 204 val L3NBanks = 4 205 val L3NWays = 8 206 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 207 208 // on chip network configurations 209 val L3BusWidth = 256 210} 211 212trait HasXSLog { this: RawModule => 213 implicit val moduleName: String = this.name 214} 215 216abstract class XSModule extends MultiIOModule 217 with HasXSParameter 218 with HasExceptionNO 219 with HasXSLog 220 with HasFPUParameters 221{ 222 def io: Record 223} 224 225//remove this trait after impl module logic 226trait NeedImpl { this: RawModule => 227 override protected def IO[T <: Data](iodef: T): T = { 228 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 229 val io = chisel3.experimental.IO(iodef) 230 io <> DontCare 231 io 232 } 233} 234 235abstract class XSBundle extends Bundle 236 with HasXSParameter 237 238case class EnviromentParameters 239( 240 FPGAPlatform: Boolean = true, 241 EnableDebug: Boolean = false 242) 243 244object AddressSpace extends HasXSParameter { 245 // (start, size) 246 // address out of MMIO will be considered as DRAM 247 def mmio = List( 248 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 249 (0x40000000L, 0x40000000L) // external devices 250 ) 251 252 def isMMIO(addr: UInt): Bool = mmio.map(range => { 253 require(isPow2(range._2)) 254 val bits = log2Up(range._2) 255 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 256 }).reduce(_ || _) 257} 258 259 260 261class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 262 263 // outer facing nodes 264 val dcache = LazyModule(new DCache()) 265 val uncache = LazyModule(new Uncache()) 266 val l1pluscache = LazyModule(new L1plusCache()) 267 val ptw = LazyModule(new PTW()) 268 269 lazy val module = new XSCoreImp(this) 270} 271 272class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 273 with HasXSParameter 274 with HasExeBlockHelper 275{ 276 val io = IO(new Bundle { 277 val externalInterrupt = new ExternalInterruptIO 278 }) 279 280 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 281 282 // to fast wake up fp, mem rs 283 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 284 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 285 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 286 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 287 288 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 289 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 290 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 291 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 292 293 val frontend = Module(new Frontend) 294 val ctrlBlock = Module(new CtrlBlock) 295 val integerBlock = Module(new IntegerBlock( 296 fastWakeUpIn = fpBlockFastWakeUpInt, 297 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 298 fastFpOut = intBlockFastWakeUpFp, 299 slowFpOut = intBlockSlowWakeUpFp, 300 fastIntOut = intBlockFastWakeUpInt, 301 slowIntOut = intBlockSlowWakeUpInt 302 )) 303 val floatBlock = Module(new FloatBlock( 304 fastWakeUpIn = intBlockFastWakeUpFp, 305 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 306 fastFpOut = fpBlockFastWakeUpFp, 307 slowFpOut = fpBlockSlowWakeUpFp, 308 fastIntOut = fpBlockFastWakeUpInt, 309 slowIntOut = fpBlockSlowWakeUpInt 310 )) 311 val memBlock = Module(new MemBlock( 312 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 313 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 314 fastFpOut = Seq(), 315 slowFpOut = loadExuConfigs, 316 fastIntOut = Seq(), 317 slowIntOut = loadExuConfigs 318 )) 319 320 val dcache = outer.dcache.module 321 val uncache = outer.uncache.module 322 val l1pluscache = outer.l1pluscache.module 323 val ptw = outer.ptw.module 324 325 326 frontend.io.backend <> ctrlBlock.io.frontend 327 frontend.io.sfence <> integerBlock.io.fenceio.sfence 328 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 329 330 frontend.io.icacheMemAcq <> l1pluscache.io.req 331 l1pluscache.io.resp <> frontend.io.icacheMemGrant 332 l1pluscache.io.flush := frontend.io.l1plusFlush 333 frontend.io.fencei := integerBlock.io.fenceio.fencei 334 335 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 336 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 337 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 338 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 339 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 340 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 341 342 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 343 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 344 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 345 346 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 347 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 348 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 349 350 351 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 352 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 353 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 354 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 355 356 val wakeUpMem = Seq( 357 integerBlock.io.wakeUpIntOut, 358 integerBlock.io.wakeUpFpOut, 359 floatBlock.io.wakeUpIntOut, 360 floatBlock.io.wakeUpFpOut 361 ) 362 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 363 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 364 val raw = WireInit(f) 365 raw 366 })) 367 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 368 val raw = WireInit(s) 369 raw 370 })) 371 372 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 373 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 374 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 375 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 376 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 377 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 378 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 379 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 380 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 381 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 382 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 383 384 floatBlock.io.frm <> integerBlock.io.csrio.frm 385 386 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 387 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 388 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 389 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 390 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 391 392 ptw.io.tlb(0) <> memBlock.io.ptw 393 ptw.io.tlb(1) <> frontend.io.ptw 394 ptw.io.sfence <> integerBlock.io.fenceio.sfence 395 ptw.io.csr <> integerBlock.io.csrio.tlb 396 397 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 398 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 399 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 400 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 401 uncache.io.lsq <> memBlock.io.dcache.uncache 402 403 if (!env.FPGAPlatform) { 404 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 405 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 406 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 407 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 408 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 409 } 410 411} 412