xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 125414a14d93cb981498e961285d11b193bc32bf) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Config
9import xiangshan.backend.exu.ExuConfig
10import xiangshan.frontend.Frontend
11import xiangshan.utils._
12
13trait HasXSParameter {
14  val LogLevel = XSLogLevel.ALL
15  val XLEN = 64
16  val HasMExtension = true
17  val HasCExtension = true
18  val HasDiv = true
19  val HasIcache = true
20  val HasDcache = true
21  val EnableStoreQueue = false
22  val AddrBits = 64 // AddrBits is used in some cases
23  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
24  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
25  val AddrBytes = AddrBits / 8 // unused
26  val DataBits = XLEN
27  val DataBytes = DataBits / 8
28  val HasFPU = true
29  val FetchWidth = 8
30  val IBufSize = 64
31  val DecodeWidth = 8
32  val DecBufSize = 8
33  val RenameWidth = 6
34  val CommitWidth = 6
35  val BrqSize = 16
36  val BrTagWidth = log2Up(BrqSize)
37  val NRPhyRegs = 128
38  val PhyRegIdxWidth = log2Up(NRPhyRegs)
39  val NRReadPorts = 14
40  val NRWritePorts = 8
41  val RoqSize = 32
42  val RoqIdxWidth = log2Up(RoqSize)
43  val ExtendedRoqIdxWidth = RoqIdxWidth + 1
44  val IntDqDeqWidth = 4
45  val FpDqDeqWidth = 4
46  val LsDqDeqWidth = 4
47  val dp1Config = DP1Config(
48    IntDqSize = 16,
49    FpDqSize = 16,
50    LsDqSize = 16
51  )
52  val exuConfig = ExuConfig(
53    AluCnt = 4,
54    BruCnt = 1,
55    MulCnt = 1,
56    MduCnt = 1,
57    FmacCnt = 4,
58    FmiscCnt = 1,
59    FmiscDivSqrtCnt = 1,
60    LduCnt = 1,
61    StuCnt = 1
62  )
63}
64
65trait HasXSLog { this: Module =>
66  implicit val _implict_module = this
67}
68
69abstract class XSModule extends Module
70  with HasXSParameter
71  with HasExceptionNO
72  with HasXSLog
73
74//remove this trait after impl module logic
75trait NeedImpl { this: Module =>
76  override protected def IO[T <: Data](iodef: T): T = {
77    val io = chisel3.experimental.IO(iodef)
78    io <> DontCare
79    io
80  }
81}
82
83abstract class XSBundle extends Bundle
84  with HasXSParameter
85
86case class XSConfig
87(
88  FPGAPlatform: Boolean = true,
89  EnableDebug: Boolean = false
90)
91
92class XSCore(implicit val p: XSConfig) extends XSModule {
93  val io = IO(new Bundle {
94    val imem = new SimpleBusC
95    val dmem = new SimpleBusC
96    val mmio = new SimpleBusUC
97    val frontend = Flipped(new SimpleBusUC())
98  })
99
100  io.imem <> DontCare
101
102  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
103
104  val front = Module(new Frontend)
105  val backend = Module(new Backend)
106
107  front.io.backend <> backend.io.frontend
108
109  backend.io.memMMU.imem <> DontCare
110
111  val dtlb = TLB(
112    in = backend.io.dmem,
113    mem = dmemXbar.io.in(1),
114    flush = false.B,
115    csrMMU = backend.io.memMMU.dmem
116  )(TLBConfig(name = "dtlb", totalEntry = 64))
117  dmemXbar.io.in(0) <> dtlb.io.out
118  dmemXbar.io.in(2) <> io.frontend
119
120  io.dmem <> Cache(
121    in = dmemXbar.io.out,
122    mmio = Seq(io.mmio),
123    flush = "b00".U,
124    empty = dtlb.io.cacheEmpty,
125    enable = HasDcache
126  )(CacheConfig(name = "dcache"))
127}
128