1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import freechips.rocketchip.tilelink.TLBuffer 27import system.HasSoCParameter 28import utility._ 29import utils._ 30import xiangshan.backend._ 31import xiangshan.cache.mmu._ 32import xiangshan.frontend._ 33import xiangshan.v2backend._ 34 35abstract class XSModule(implicit val p: Parameters) extends Module 36 with HasXSParameter 37 with HasFPUParameters 38 39//remove this trait after impl module logic 40trait NeedImpl { 41 this: RawModule => 42 override protected def IO[T <: Data](iodef: T): T = { 43 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 44 val io = chisel3.experimental.IO(iodef) 45 io <> DontCare 46 io 47 } 48} 49 50abstract class XSBundle(implicit val p: Parameters) extends Bundle 51 with HasXSParameter 52 53abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 54 with HasXSParameter 55{ 56 // interrupt sinks 57 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 58 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 59 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 60 // outer facing nodes 61 val frontend = LazyModule(new Frontend()) 62 val ptw = LazyModule(new L2TLBWrapper()) 63 val ptw_to_l2_buffer = if (!coreParams.softPTW) LazyModule(new TLBuffer) else null 64 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 65 val backend = LazyModule(new Backend(backendParams)) 66 67 if (!coreParams.softPTW) { 68 ptw_to_l2_buffer.node := ptw.node 69 } 70 71 val memBlock = LazyModule(new MemBlock()(p.alter((site, here, up) => { 72 case XSCoreParamsKey => up(XSCoreParamsKey).copy( 73 IssQueSize = 16 // Todo 74 ) 75 }))) 76} 77 78class XSCore()(implicit p: config.Parameters) extends XSCoreBase 79 with HasXSDts 80{ 81 lazy val module = new XSCoreImp(this) 82} 83 84class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 85 with HasXSParameter 86 with HasSoCParameter { 87 val io = IO(new Bundle { 88 val hartId = Input(UInt(64.W)) 89 val reset_vector = Input(UInt(PAddrBits.W)) 90 val cpu_halt = Output(Bool()) 91 val l2_pf_enable = Output(Bool()) 92 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 93 val beu_errors = Output(new XSL1BusErrors()) 94 }) 95 96 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 97 98 val frontend = outer.frontend.module 99 val backend = outer.backend.module 100 val memBlock = outer.memBlock.module 101 val ptw = outer.ptw.module 102 val ptw_to_l2_buffer = if (!coreParams.softPTW) outer.ptw_to_l2_buffer.module else null 103 104 val fenceio = backend.io.fenceio 105 106 frontend.io.hartId := io.hartId 107 frontend.io.backend <> backend.io.frontend 108 frontend.io.sfence <> backend.io.frontendSfence 109 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 110 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 111 frontend.io.fencei <> fenceio.fencei 112 113 backend.io.fromTop.hartId := io.hartId 114 backend.io.fromTop.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 115 backend.io.fromTop.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 116 backend.io.fromTop.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 117 backend.io.fromTop.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 118 backend.io.fromTop.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 119 120 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 121 122 backend.io.mem.stIn.zip(memBlock.io.stIn).foreach { case (sink, source) => 123 sink.valid := source.valid 124 sink.bits := 0.U.asTypeOf(sink.bits) 125 sink.bits.robIdx := source.bits.uop.robIdx 126 sink.bits.ssid := source.bits.uop.ssid 127 sink.bits.storeSetHit := source.bits.uop.storeSetHit 128 // The other signals have not been used 129 } 130 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 131 backend.io.mem.lsqEnqIO <> memBlock.io.enqLsq 132 backend.io.mem.sqDeq := memBlock.io.sqDeq 133 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 134 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 135 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 136 backend.io.mem.writeBack <> memBlock.io.writeback 137 138 frontend.io.reset_vector := io.reset_vector 139 140 io.cpu_halt := backend.io.toTop.cpuHalted 141 142 // memblock error exception writeback, 1 cycle after normal writeback 143 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 144 145 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 146 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 147 148 memBlock.io.hartId := io.hartId 149 memBlock.io.issue <> backend.io.mem.issueUops 150 // By default, instructions do not have exceptions when they enter the function units. 151 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 152 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 153 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 154 backend.io.mem.exceptionVAddr := memBlock.io.lsqio.exceptionAddr.vaddr 155 backend.io.mem.csrDistributedUpdate := memBlock.io.csrUpdate 156 157 backend.io.perf.frontendInfo := frontend.io.frontendInfo 158 backend.io.perf.memInfo := memBlock.io.memInfo 159 backend.io.perf.perfEventsFrontend := frontend.getPerf 160 backend.io.perf.perfEventsLsu := memBlock.getPerf 161 backend.io.perf.perfEventsHc := io.perfEvents 162 163 // XSPerfHistogram("fastIn_count", PopCount(allFastUop1.map(_.valid)), true.B, 0, allFastUop1.length, 1) 164// XSPerfHistogram("wakeup_count", PopCount(rfWriteback.map(_.valid)), true.B, 0, rfWriteback.length, 1) 165 166// ctrlBlock.perfinfo.perfEventsEu0 := intExuBlock.getPerf.dropRight(outer.intExuBlock.scheduler.numRs) 167// ctrlBlock.perfinfo.perfEventsEu1 := vecExuBlock.getPerf.dropRight(outer.vecExuBlock.scheduler.numRs) 168 if (!coreParams.softPTW) { 169 memBlock.io.perfEventsPTW := ptw.getPerf 170 } else { 171 memBlock.io.perfEventsPTW := DontCare 172 } 173// ctrlBlock.perfinfo.perfEventsRs := outer.exuBlocks.flatMap(b => b.module.getPerf.takeRight(b.scheduler.numRs)) 174 175 memBlock.io.sfence <> backend.io.mem.sfence 176 memBlock.io.fenceToSbuffer <> backend.io.mem.toSbuffer 177 178 memBlock.io.redirect <> backend.io.mem.redirect 179 memBlock.io.rsfeedback <> backend.io.mem.rsFeedBack 180 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 181 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 182 memBlock.io.lsqio.rob <> backend.io.mem.robLsqIO 183 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 184 185 val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay,frontend.io.ptw, fenceio.sfence, backend.io.tlb, l2tlbParams.ifilterSize) 186 val itlbRepeater2 = PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, ptw.io.tlb(0), fenceio.sfence, backend.io.tlb) 187 val dtlbRepeater1 = PTWFilter(ldtlbParams.fenceDelay, memBlock.io.ptw, fenceio.sfence, backend.io.tlb, l2tlbParams.dfilterSize) 188 val dtlbRepeater2 = PTWRepeaterNB(passReady = false, ldtlbParams.fenceDelay, dtlbRepeater1.io.ptw, ptw.io.tlb(1), fenceio.sfence, backend.io.tlb) 189 ptw.io.sfence <> fenceio.sfence 190 ptw.io.csr.tlb <> backend.io.tlb 191 ptw.io.csr.distribute_csr <> backend.io.csrCustomCtrl.distribute_csr 192 193 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 194 io.l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 195 196 // Modules are reset one by one 197 val resetTree = ResetGenNode( 198 Seq( 199 ModuleNode(memBlock), ModuleNode(dtlbRepeater1), 200 ResetGenNode(Seq( 201 ModuleNode(itlbRepeater2), 202 ModuleNode(ptw), 203 ModuleNode(dtlbRepeater2), 204 ModuleNode(ptw_to_l2_buffer), 205 )), 206 ResetGenNode(Seq( 207 ModuleNode(backend), 208 ResetGenNode(Seq( 209 ResetGenNode(Seq( 210 ModuleNode(frontend), ModuleNode(itlbRepeater1) 211 )) 212 )) 213 )) 214 ) 215 ) 216 217 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 218 219} 220