xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 0be64786e3f92090f2feec39645c2052ed97cd82) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import top.Parameters
6import xiangshan.backend._
7import xiangshan.backend.dispatch.DispatchParameters
8import xiangshan.backend.exu.ExuParameters
9import xiangshan.backend.exu.Exu._
10import xiangshan.frontend._
11import xiangshan.mem._
12import xiangshan.backend.fu.HasExceptionNO
13import xiangshan.cache.{DCache, InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater, Uncache, MemoryOpConstants, MissReq}
14import xiangshan.cache.prefetch._
15import chipsalliance.rocketchip.config
16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar}
18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker}
21import freechips.rocketchip.tile.HasFPUParameters
22import sifive.blocks.inclusivecache.PrefetcherIO
23import utils._
24
25object hartIdCore extends (() => Int) {
26  var x = 0
27
28  def apply(): Int = {
29    x = x + 1
30    x - 1
31  }
32}
33
34case class XSCoreParameters
35(
36  XLEN: Int = 64,
37  HasMExtension: Boolean = true,
38  HasCExtension: Boolean = true,
39  HasDiv: Boolean = true,
40  HasICache: Boolean = true,
41  HasDCache: Boolean = true,
42  EnableStoreQueue: Boolean = true,
43  AddrBits: Int = 64,
44  VAddrBits: Int = 39,
45  PAddrBits: Int = 40,
46  HasFPU: Boolean = true,
47  FetchWidth: Int = 8,
48  EnableBPU: Boolean = true,
49  EnableBPD: Boolean = true,
50  EnableRAS: Boolean = true,
51  EnableLB: Boolean = false,
52  EnableLoop: Boolean = true,
53  EnableSC: Boolean = false,
54  EnbaleTlbDebug: Boolean = false,
55  EnableJal: Boolean = false,
56  EnableUBTB: Boolean = true,
57  HistoryLength: Int = 64,
58  BtbSize: Int = 2048,
59  JbtacSize: Int = 1024,
60  JbtacBanks: Int = 8,
61  RasSize: Int = 16,
62  CacheLineSize: Int = 512,
63  UBtbWays: Int = 16,
64  BtbWays: Int = 2,
65
66  EnableL1plusPrefetcher: Boolean = true,
67  IBufSize: Int = 32,
68  DecodeWidth: Int = 6,
69  RenameWidth: Int = 6,
70  CommitWidth: Int = 6,
71  BrqSize: Int = 32,
72  FtqSize: Int = 48,
73  IssQueSize: Int = 12,
74  NRPhyRegs: Int = 160,
75  NRIntReadPorts: Int = 14,
76  NRIntWritePorts: Int = 8,
77  NRFpReadPorts: Int = 14,
78  NRFpWritePorts: Int = 8,
79  LoadQueueSize: Int = 64,
80  StoreQueueSize: Int = 48,
81  RoqSize: Int = 192,
82  dpParams: DispatchParameters = DispatchParameters(
83    IntDqSize = 16,
84    FpDqSize = 16,
85    LsDqSize = 16,
86    IntDqDeqWidth = 4,
87    FpDqDeqWidth = 4,
88    LsDqDeqWidth = 4
89  ),
90  exuParameters: ExuParameters = ExuParameters(
91    JmpCnt = 1,
92    AluCnt = 4,
93    MulCnt = 0,
94    MduCnt = 2,
95    FmacCnt = 4,
96    FmiscCnt = 2,
97    FmiscDivSqrtCnt = 0,
98    LduCnt = 2,
99    StuCnt = 2
100  ),
101  LoadPipelineWidth: Int = 2,
102  StorePipelineWidth: Int = 2,
103  StoreBufferSize: Int = 16,
104  RefillSize: Int = 512,
105  TlbEntrySize: Int = 32,
106  TlbSPEntrySize: Int = 4,
107  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
108  PtwSPEntrySize: Int = 16,
109  PtwL1EntrySize: Int = 16,
110  PtwL2EntrySize: Int = 2048, //(256 * 8)
111  NumPerfCounters: Int = 16,
112  NrExtIntr: Int = 150,
113  PerfRealTime: Boolean = false,
114  PerfIntervalBits: Int = 15
115)
116
117trait HasXSParameter {
118
119  val core = Parameters.get.coreParameters
120  val env = Parameters.get.envParameters
121
122  val XLEN = 64
123  val minFLen = 32
124  val fLen = 64
125
126  def xLen = 64
127
128  val HasMExtension = core.HasMExtension
129  val HasCExtension = core.HasCExtension
130  val HasDiv = core.HasDiv
131  val HasIcache = core.HasICache
132  val HasDcache = core.HasDCache
133  val EnableStoreQueue = core.EnableStoreQueue
134  val AddrBits = core.AddrBits // AddrBits is used in some cases
135  val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits
136  val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits
137  val AddrBytes = AddrBits / 8 // unused
138  val DataBits = XLEN
139  val DataBytes = DataBits / 8
140  val HasFPU = core.HasFPU
141  val FetchWidth = core.FetchWidth
142  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
143  val EnableBPU = core.EnableBPU
144  val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3
145  val EnableRAS = core.EnableRAS
146  val EnableLB = core.EnableLB
147  val EnableLoop = core.EnableLoop
148  val EnableSC = core.EnableSC
149  val EnbaleTlbDebug = core.EnbaleTlbDebug
150  val HistoryLength = core.HistoryLength
151  val BtbSize = core.BtbSize
152  // val BtbWays = 4
153  val BtbBanks = PredictWidth
154  // val BtbSets = BtbSize / BtbWays
155  val JbtacSize = core.JbtacSize
156  val JbtacBanks = core.JbtacBanks
157  val RasSize = core.RasSize
158  val CacheLineSize = core.CacheLineSize
159  val CacheLineHalfWord = CacheLineSize / 16
160  val ExtHistoryLength = HistoryLength + 64
161  val UBtbWays = core.UBtbWays
162  val BtbWays = core.BtbWays
163  val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher
164  val IBufSize = core.IBufSize
165  val DecodeWidth = core.DecodeWidth
166  val RenameWidth = core.RenameWidth
167  val CommitWidth = core.CommitWidth
168  val BrqSize = core.BrqSize
169  val FtqSize = core.FtqSize
170  val IssQueSize = core.IssQueSize
171  val BrTagWidth = log2Up(BrqSize)
172  val NRPhyRegs = core.NRPhyRegs
173  val PhyRegIdxWidth = log2Up(NRPhyRegs)
174  val RoqSize = core.RoqSize
175  val LoadQueueSize = core.LoadQueueSize
176  val StoreQueueSize = core.StoreQueueSize
177  val dpParams = core.dpParams
178  val exuParameters = core.exuParameters
179  val NRIntReadPorts = core.NRIntReadPorts
180  val NRIntWritePorts = core.NRIntWritePorts
181  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
182  val NRFpReadPorts = core.NRFpReadPorts
183  val NRFpWritePorts = core.NRFpWritePorts
184  val LoadPipelineWidth = core.LoadPipelineWidth
185  val StorePipelineWidth = core.StorePipelineWidth
186  val StoreBufferSize = core.StoreBufferSize
187  val RefillSize = core.RefillSize
188  val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth
189  val TlbEntrySize = core.TlbEntrySize
190  val TlbSPEntrySize = core.TlbSPEntrySize
191  val PtwL3EntrySize = core.PtwL3EntrySize
192  val PtwSPEntrySize = core.PtwSPEntrySize
193  val PtwL1EntrySize = core.PtwL1EntrySize
194  val PtwL2EntrySize = core.PtwL2EntrySize
195  val NumPerfCounters = core.NumPerfCounters
196  val NrExtIntr = core.NrExtIntr
197  val PerfRealTime = core.PerfRealTime
198  val PerfIntervalBits = core.PerfIntervalBits
199
200  val instBytes = if (HasCExtension) 2 else 4
201  val instOffsetBits = log2Ceil(instBytes)
202
203  val icacheParameters = ICacheParameters(
204    tagECC = Some("parity"),
205    dataECC = Some("parity"),
206    replacer = Some("setlru"),
207    nMissEntries = 2
208  )
209
210  val l1plusCacheParameters = L1plusCacheParameters(
211    tagECC = Some("secded"),
212    dataECC = Some("secded"),
213    nMissEntries = 8
214  )
215
216  val dcacheParameters = DCacheParameters(
217    tagECC = Some("secded"),
218    dataECC = Some("secded"),
219    nMissEntries = 16,
220    nProbeEntries = 16,
221    nReleaseEntries = 16,
222    nStoreReplayEntries = 16
223  )
224
225  val LRSCCycles = 100
226
227
228  // cache hierarchy configurations
229  val l1BusDataWidth = 256
230
231  // L2 configurations
232  val L1BusWidth = 256
233  val L2Size = 512 * 1024 // 512KB
234  val L2BlockSize = 64
235  val L2NWays = 8
236  val L2NSets = L2Size / L2BlockSize / L2NWays
237
238  // L3 configurations
239  val L2BusWidth = 256
240  val L3Size = 4 * 1024 * 1024 // 4MB
241  val L3BlockSize = 64
242  val L3NBanks = 4
243  val L3NWays = 8
244  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
245
246  // on chip network configurations
247  val L3BusWidth = 256
248
249  // icache prefetcher
250  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
251    enable = true,
252    _type = "stream",
253    streamParams = StreamPrefetchParameters(
254      streamCnt = 2,
255      streamSize = 4,
256      ageWidth = 4,
257      blockBytes = l1plusCacheParameters.blockBytes,
258      reallocStreamOnMissInstantly = true,
259      cacheName = "icache"
260    )
261  )
262
263  // dcache prefetcher
264  val l2PrefetcherParameters = L2PrefetcherParameters(
265    enable = true,
266    _type = "bop", // "stream" or "bop"
267    streamParams = StreamPrefetchParameters(
268      streamCnt = 4,
269      streamSize = 4,
270      ageWidth = 4,
271      blockBytes = L2BlockSize,
272      reallocStreamOnMissInstantly = true,
273      cacheName = "dcache"
274    ),
275    bopParams = BOPParameters(
276      rrTableEntries = 256,
277      rrTagBits = 12,
278      scoreBits = 5,
279      roundMax = 50,
280      badScore = 1,
281      blockBytes = L2BlockSize,
282      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
283    ),
284  )
285}
286
287trait HasXSLog {
288  this: RawModule =>
289  implicit val moduleName: String = this.name
290}
291
292abstract class XSModule extends MultiIOModule
293  with HasXSParameter
294  with HasExceptionNO
295  with HasXSLog
296  with HasFPUParameters {
297  def io: Record
298}
299
300//remove this trait after impl module logic
301trait NeedImpl {
302  this: RawModule =>
303  override protected def IO[T <: Data](iodef: T): T = {
304    println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module")
305    val io = chisel3.experimental.IO(iodef)
306    io <> DontCare
307    io
308  }
309}
310
311abstract class XSBundle extends Bundle
312  with HasXSParameter
313
314case class EnviromentParameters
315(
316  FPGAPlatform: Boolean = true,
317  EnableDebug: Boolean = false,
318  EnablePerfDebug: Boolean = true,
319  DualCore: Boolean = false
320)
321
322// object AddressSpace extends HasXSParameter {
323//   // (start, size)
324//   // address out of MMIO will be considered as DRAM
325//   def mmio = List(
326//     (0x00000000L, 0x40000000L),  // internal devices, such as CLINT and PLIC
327//     (0x40000000L, 0x40000000L)   // external devices
328//   )
329
330//   def isMMIO(addr: UInt): Bool = mmio.map(range => {
331//     require(isPow2(range._2))
332//     val bits = log2Up(range._2)
333//     (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
334//   }).reduce(_ || _)
335// }
336
337
338class XSCore()(implicit p: config.Parameters) extends LazyModule
339  with HasXSParameter
340  with HasExeBlockHelper {
341  // outer facing nodes
342  val frontend = LazyModule(new Frontend())
343  val l1pluscache = LazyModule(new L1plusCache())
344  val ptw = LazyModule(new PTW())
345  val memBlock = LazyModule(new MemBlock(
346    fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency),
347    slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs,
348    fastWakeUpOut = Seq(),
349    slowWakeUpOut = loadExuConfigs
350  ))
351
352  lazy val module = new XSCoreImp(this)
353}
354
355class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
356  with HasXSParameter
357  with HasExeBlockHelper {
358  val io = IO(new Bundle {
359    val hartId = Input(UInt(64.W))
360    val externalInterrupt = new ExternalInterruptIO
361    val l2_pf_enable = Output(Bool())
362  })
363
364  val difftestIO = IO(new DifftestBundle())
365  difftestIO <> DontCare
366
367  val trapIO = IO(new TrapIO())
368  trapIO <> DontCare
369
370  println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
371  AddressSpace.checkMemmap()
372  AddressSpace.printMemmap()
373
374  // to fast wake up fp, mem rs
375  val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency)
376  val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency)
377
378  val ctrlBlock = Module(new CtrlBlock)
379  val integerBlock = Module(new IntegerBlock(
380    fastWakeUpIn = Seq(),
381    slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs,
382    fastWakeUpOut = intBlockFastWakeUp,
383    slowWakeUpOut = intBlockSlowWakeUp
384  ))
385  val floatBlock = Module(new FloatBlock(
386    intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf),
387    memSlowWakeUpIn = loadExuConfigs,
388    fastWakeUpOut = Seq(),
389    slowWakeUpOut = fpExuConfigs
390  ))
391
392  val frontend = outer.frontend.module
393  val memBlock = outer.memBlock.module
394  val l1pluscache = outer.l1pluscache.module
395  val ptw = outer.ptw.module
396
397  frontend.io.backend <> ctrlBlock.io.frontend
398  frontend.io.sfence <> integerBlock.io.fenceio.sfence
399  frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
400  frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl
401
402  frontend.io.icacheMemAcq <> l1pluscache.io.req
403  l1pluscache.io.resp <> frontend.io.icacheMemGrant
404  l1pluscache.io.flush := frontend.io.l1plusFlush
405  frontend.io.fencei := integerBlock.io.fenceio.fencei
406
407  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
408  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
409  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
410  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
411  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
412  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
413  ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl
414
415  val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(x => intOutValid(x))
416  val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(x => fpOutValid(x))
417  memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B)
418  memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B)
419
420  fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B)
421  val fpBlockWakeUpInt = fpExuConfigs
422    .zip(floatBlock.io.wakeUpOut.slow)
423    .filter(_._1.writeIntRf)
424    .map(_._2).map(x => intOutValid(x, connectReady = true))
425
426  intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B)
427  val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency)
428    .zip(integerBlock.io.wakeUpOut.slow)
429    .filter(_._1.writeFpRf)
430    .map(_._2).map(x => fpOutValid(x, connectReady = true))
431
432  integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt
433  integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
434
435  floatBlock.io.intWakeUpFp <> intBlockWakeUpFp
436  floatBlock.io.memWakeUpFp <> memBlockWakeUpFp
437  floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
438
439  val wakeUpMem = Seq(
440    integerBlock.io.wakeUpOut,
441    floatBlock.io.wakeUpOut,
442  )
443  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
444  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast)
445  // Note: 'WireInit' is used to block 'ready's from memBlock,
446  // we don't need 'ready's from memBlock
447  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x)))
448
449  integerBlock.io.csrio.hartId <> io.hartId
450  integerBlock.io.csrio.perf <> DontCare
451  integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr
452  integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags
453  integerBlock.io.csrio.fpu.isIllegal := false.B
454  integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
455  integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm
456  integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
457  integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet
458  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
459  integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
460  integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
461  integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
462
463  integerBlock.io.fenceio.sfence <> memBlock.io.sfence
464  integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
465
466  memBlock.io.tlbCsr <> RegNext(integerBlock.io.csrio.tlb)
467  memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
468  memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx
469  memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
470  memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType)
471
472  val itlbRepester = Module(new PTWRepeater())
473  val dtlbRepester = Module(new PTWRepeater())
474  itlbRepester.io.tlb <> frontend.io.ptw
475  dtlbRepester.io.tlb <> memBlock.io.ptw
476  itlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
477  dtlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
478  ptw.io.tlb(0) <> dtlbRepester.io.ptw
479  ptw.io.tlb(1) <> itlbRepester.io.ptw
480  ptw.io.sfence <> integerBlock.io.fenceio.sfence
481  ptw.io.csr <> integerBlock.io.csrio.tlb
482
483  // if l2 prefetcher use stream prefetch, it should be placed in XSCore
484  assert(l2PrefetcherParameters._type == "bop")
485  io.l2_pf_enable := RegNext(integerBlock.io.csrio.customCtrl.l2_pf_enable)
486
487  if (!env.FPGAPlatform) {
488    val id = hartIdCore()
489    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
490    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
491    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
492    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
493    difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic
494    difftestIO.fromPtw <> ptw.difftestIO
495    trapIO <> ctrlBlock.trapIO
496
497    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
498    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
499    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
500    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
501    difftestIO.fromXSCore.r := debugArchReg
502  }
503
504}
505