xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 06a36b4fc9846f4cabc63aa8b4f243ab13e4d01b) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Config
9import xiangshan.backend.exu.ExuConfig
10import xiangshan.frontend.Frontend
11
12trait HasXSParameter {
13  val XLEN = 64
14  val HasMExtension = true
15  val HasCExtension = true
16  val HasDiv = true
17  val HasIcache = true
18  val HasDcache = true
19  val EnableStoreQueue = false
20  val AddrBits = 64 // AddrBits is used in some cases
21  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
22  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
23  val AddrBytes = AddrBits / 8 // unused
24  val DataBits = XLEN
25  val DataBytes = DataBits / 8
26  val HasFPU = true
27  val FetchWidth = 8
28  val IBufSize = 64
29  val DecodeWidth = 8
30  val DecBufSize = 8
31  val RenameWidth = 6
32  val CommitWidth = 6
33  val BrqSize = 16
34  val BrTagWidth = log2Up(BrqSize)
35  val NRPhyRegs = 128
36  val PhyRegIdxWidth = log2Up(NRPhyRegs)
37  val NRReadPorts = 14
38  val NRWritePorts = 8
39  val RoqSize = 32
40  val RoqIdxWidth = log2Up(RoqSize)
41  val ExtendedRoqIdxWidth = RoqIdxWidth + 1
42  val IntDqDeqWidth = 4
43  val FpDqDeqWidth = 4
44  val LsDqDeqWidth = 4
45  val dp1Config = DP1Config(
46    IntDqSize = 16,
47    FpDqSize = 16,
48    LsDqSize = 16
49  )
50  val exuConfig = ExuConfig(
51    AluCnt = 4,
52    BruCnt = 1,
53    MulCnt = 1,
54    MduCnt = 1,
55    FmacCnt = 4,
56    FmiscCnt = 1,
57    FmiscDivSqrtCnt = 1,
58    LduCnt = 1,
59    StuCnt = 1
60  )
61}
62
63abstract class XSModule extends Module
64  with HasXSParameter
65  with HasExceptionNO
66
67//remove this trait after impl module logic
68trait NeedImpl { this: Module =>
69  override protected def IO[T <: Data](iodef: T): T = {
70    val io = chisel3.experimental.IO(iodef)
71    io <> DontCare
72    io
73  }
74}
75
76abstract class XSBundle extends Bundle
77  with HasXSParameter
78
79case class XSConfig
80(
81  FPGAPlatform: Boolean = true,
82  EnableDebug: Boolean = false
83)
84
85class XSCore(implicit val p: XSConfig) extends XSModule {
86  val io = IO(new Bundle {
87    val imem = new SimpleBusC
88    val dmem = new SimpleBusC
89    val mmio = new SimpleBusUC
90    val frontend = Flipped(new SimpleBusUC())
91  })
92
93  io.imem <> DontCare
94
95  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
96
97  val front = Module(new Frontend)
98  val backend = Module(new Backend)
99
100  front.io.backend <> backend.io.frontend
101
102  backend.io.memMMU.imem <> DontCare
103
104  val dtlb = TLB(
105    in = backend.io.dmem,
106    mem = dmemXbar.io.in(1),
107    flush = false.B,
108    csrMMU = backend.io.memMMU.dmem
109  )(TLBConfig(name = "dtlb", totalEntry = 64))
110  dmemXbar.io.in(0) <> dtlb.io.out
111  dmemXbar.io.in(2) <> io.frontend
112
113  io.dmem <> Cache(
114    in = dmemXbar.io.out,
115    mmio = Seq(io.mmio),
116    flush = "b00".U,
117    empty = dtlb.io.cacheEmpty,
118    enable = HasDcache
119  )(CacheConfig(name = "dcache"))
120}
121