1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 6import top.Parameters 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DispatchParameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.cache.{ICache, DCache, DCacheParameters, ICacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = false, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = true, 36 EnableLB: Boolean = false, 37 EnableLoop: Boolean = false, 38 HistoryLength: Int = 64, 39 BtbSize: Int = 2048, 40 JbtacSize: Int = 1024, 41 JbtacBanks: Int = 8, 42 RasSize: Int = 16, 43 CacheLineSize: Int = 512, 44 UBtbWays: Int = 16, 45 BtbWays: Int = 2, 46 IBufSize: Int = 64, 47 DecodeWidth: Int = 6, 48 RenameWidth: Int = 6, 49 CommitWidth: Int = 6, 50 BrqSize: Int = 16, 51 IssQueSize: Int = 8, 52 NRPhyRegs: Int = 128, 53 NRIntReadPorts: Int = 8, 54 NRIntWritePorts: Int = 8, 55 NRFpReadPorts: Int = 14, 56 NRFpWritePorts: Int = 8, 57 EnableUnifiedLSQ: Boolean = true, 58 LsroqSize: Int = 16, 59 LoadQueueSize: Int = 16, 60 StoreQueueSize: Int = 16, 61 RoqSize: Int = 32, 62 dpParams: DispatchParameters = DispatchParameters( 63 DqEnqWidth = 4, 64 IntDqSize = 64, 65 FpDqSize = 64, 66 LsDqSize = 64, 67 IntDqDeqWidth = 4, 68 FpDqDeqWidth = 4, 69 LsDqDeqWidth = 4, 70 IntDqReplayWidth = 4, 71 FpDqReplayWidth = 4, 72 LsDqReplayWidth = 4 73 ), 74 exuParameters: ExuParameters = ExuParameters( 75 JmpCnt = 1, 76 AluCnt = 4, 77 MulCnt = 0, 78 MduCnt = 2, 79 FmacCnt = 0, 80 FmiscCnt = 0, 81 FmiscDivSqrtCnt = 0, 82 LduCnt = 2, 83 StuCnt = 2 84 ), 85 LoadPipelineWidth: Int = 2, 86 StorePipelineWidth: Int = 2, 87 StoreBufferSize: Int = 16, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbL2EntrySize: Int = 256, // or 512 91 PtwL1EntrySize: Int = 16, 92 PtwL2EntrySize: Int = 256 93) 94 95trait HasXSParameter { 96 97 val core = Parameters.get.coreParameters 98 val env = Parameters.get.envParameters 99 100 val XLEN = core.XLEN 101 val HasMExtension = core.HasMExtension 102 val HasCExtension = core.HasCExtension 103 val HasDiv = core.HasDiv 104 val HasIcache = core.HasICache 105 val HasDcache = core.HasDCache 106 val EnableStoreQueue = core.EnableStoreQueue 107 val AddrBits = core.AddrBits // AddrBits is used in some cases 108 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 109 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 110 val AddrBytes = AddrBits / 8 // unused 111 val DataBits = XLEN 112 val DataBytes = DataBits / 8 113 val HasFPU = core.HasFPU 114 val FetchWidth = core.FectchWidth 115 val PredictWidth = FetchWidth * 2 116 val EnableBPU = core.EnableBPU 117 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 118 val EnableRAS = core.EnableRAS 119 val EnableLB = core.EnableLB 120 val EnableLoop = core.EnableLoop 121 val HistoryLength = core.HistoryLength 122 val BtbSize = core.BtbSize 123 // val BtbWays = 4 124 val BtbBanks = PredictWidth 125 // val BtbSets = BtbSize / BtbWays 126 val JbtacSize = core.JbtacSize 127 val JbtacBanks = core.JbtacBanks 128 val RasSize = core.RasSize 129 val CacheLineSize = core.CacheLineSize 130 val CacheLineHalfWord = CacheLineSize / 16 131 val ExtHistoryLength = HistoryLength + 64 132 val UBtbWays = core.UBtbWays 133 val BtbWays = core.BtbWays 134 val IBufSize = core.IBufSize 135 val DecodeWidth = core.DecodeWidth 136 val RenameWidth = core.RenameWidth 137 val CommitWidth = core.CommitWidth 138 val BrqSize = core.BrqSize 139 val IssQueSize = core.IssQueSize 140 val BrTagWidth = log2Up(BrqSize) 141 val NRPhyRegs = core.NRPhyRegs 142 val PhyRegIdxWidth = log2Up(NRPhyRegs) 143 val EnableUnifiedLSQ = core.EnableUnifiedLSQ 144 val LsroqSize = core.LsroqSize // 64 145 val LoadQueueSize = core.LoadQueueSize 146 val StoreQueueSize = core.StoreQueueSize 147 val RoqSize = core.RoqSize 148 val InnerRoqIdxWidth = log2Up(RoqSize) 149 val RoqIdxWidth = InnerRoqIdxWidth + 1 150 val InnerLsroqIdxWidth = log2Up(LsroqSize) 151 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 152 val dpParams = core.dpParams 153 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 154 val exuParameters = core.exuParameters 155 val NRIntReadPorts = core.NRIntReadPorts 156 val NRIntWritePorts = core.NRIntWritePorts 157 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 158 val NRFpReadPorts = core.NRFpReadPorts 159 val NRFpWritePorts = core.NRFpWritePorts 160 val LoadPipelineWidth = core.LoadPipelineWidth 161 val StorePipelineWidth = core.StorePipelineWidth 162 val StoreBufferSize = core.StoreBufferSize 163 val RefillSize = core.RefillSize 164 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 165 val TlbEntrySize = core.TlbEntrySize 166 val TlbL2EntrySize = core.TlbL2EntrySize 167 val PtwL1EntrySize = core.PtwL1EntrySize 168 val PtwL2EntrySize = core.PtwL2EntrySize 169 170 val l1BusDataWidth = 256 171 172 val icacheParameters = ICacheParameters( 173 ) 174 175 val LRSCCycles = 100 176 val dcacheParameters = DCacheParameters( 177 tagECC = Some("secded"), 178 dataECC = Some("secded"), 179 nMissEntries = 16, 180 nLoadMissEntries = 8, 181 nStoreMissEntries = 8 182 ) 183} 184 185trait HasXSLog { this: RawModule => 186 implicit val moduleName: String = this.name 187} 188 189abstract class XSModule extends Module 190 with HasXSParameter 191 with HasExceptionNO 192 with HasXSLog 193 194//remove this trait after impl module logic 195trait NeedImpl { this: Module => 196 override protected def IO[T <: Data](iodef: T): T = { 197 val io = chisel3.experimental.IO(iodef) 198 io <> DontCare 199 io 200 } 201} 202 203abstract class XSBundle extends Bundle 204 with HasXSParameter 205 206case class EnviromentParameters 207( 208 FPGAPlatform: Boolean = true, 209 EnableDebug: Boolean = false 210) 211 212object AddressSpace extends HasXSParameter { 213 // (start, size) 214 // address out of MMIO will be considered as DRAM 215 def mmio = List( 216 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 217 (0x40000000L, 0x40000000L) // external devices 218 ) 219 220 def isMMIO(addr: UInt): Bool = mmio.map(range => { 221 require(isPow2(range._2)) 222 val bits = log2Up(range._2) 223 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 224 }).reduce(_ || _) 225} 226 227 228 229class XSCore()(implicit p: config.Parameters) extends LazyModule { 230 231 val dcache = LazyModule(new DCache()) 232 val uncache = LazyModule(new Uncache()) 233 val icache = LazyModule(new ICache()) 234 val ptw = LazyModule(new PTW()) 235 236 val mem = TLIdentityNode() 237 val mmio = uncache.clientNode 238 239 // TODO: refactor these params 240 private val l2 = LazyModule(new InclusiveCache( 241 CacheParameters( 242 level = 2, 243 ways = 4, 244 sets = 512 * 1024 / (64 * 4), 245 blockBytes = 64, 246 beatBytes = 32 // beatBytes = l1BusDataWidth / 8 247 ), 248 InclusiveCacheMicroParameters( 249 writeBytes = 8 250 ) 251 )) 252 253 private val xbar = TLXbar() 254 255 xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 256 xbar := TLBuffer() := DebugIdentityNode() := icache.clientNode 257 xbar := TLBuffer() := DebugIdentityNode() := ptw.node 258 259 l2.node := xbar 260 261 mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node 262 263 lazy val module = new XSCoreImp(this) 264} 265 266class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 267 268 val front = Module(new Frontend) 269 val backend = Module(new Backend) 270 val mem = Module(new Memend) 271 272 val dcache = outer.dcache.module 273 val uncache = outer.uncache.module 274 val icache = outer.icache.module 275 val ptw = outer.ptw.module 276 277 // TODO: connect this 278 279 front.io.backend <> backend.io.frontend 280 front.io.icacheResp <> icache.io.resp 281 front.io.icacheToTlb <> icache.io.tlb 282 icache.io.req <> front.io.icacheReq 283 icache.io.flush <> front.io.icacheFlush 284 mem.io.backend <> backend.io.mem 285 286 ptw.io.tlb(0) <> mem.io.ptw 287 ptw.io.tlb(1) <> front.io.ptw 288 289 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 290 dcache.io.lsu.lsroq <> mem.io.loadMiss 291 dcache.io.lsu.atomics <> mem.io.atomics 292 dcache.io.lsu.store <> mem.io.sbufferToDcache 293 uncache.io.lsroq <> mem.io.uncache 294 295} 296