1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 6import top.Parameters 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DispatchParameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.cache.{ICache, DCache, DCacheParameters, ICacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = false, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = true, 36 EnableLB: Boolean = false, 37 EnableLoop: Boolean = false, 38 HistoryLength: Int = 64, 39 BtbSize: Int = 2048, 40 JbtacSize: Int = 1024, 41 JbtacBanks: Int = 8, 42 RasSize: Int = 16, 43 CacheLineSize: Int = 512, 44 UBtbWays: Int = 16, 45 BtbWays: Int = 2, 46 IBufSize: Int = 64, 47 DecodeWidth: Int = 6, 48 RenameWidth: Int = 6, 49 CommitWidth: Int = 6, 50 BrqSize: Int = 16, 51 IssQueSize: Int = 8, 52 NRPhyRegs: Int = 128, 53 NRIntReadPorts: Int = 8, 54 NRIntWritePorts: Int = 8, 55 NRFpReadPorts: Int = 14, 56 NRFpWritePorts: Int = 8, 57 LsroqSize: Int = 16, 58 RoqSize: Int = 32, 59 dpParams: DispatchParameters = DispatchParameters( 60 DqEnqWidth = 4, 61 IntDqSize = 64, 62 FpDqSize = 64, 63 LsDqSize = 64, 64 IntDqDeqWidth = 4, 65 FpDqDeqWidth = 4, 66 LsDqDeqWidth = 4, 67 IntDqReplayWidth = 4, 68 FpDqReplayWidth = 4, 69 LsDqReplayWidth = 4 70 ), 71 exuParameters: ExuParameters = ExuParameters( 72 JmpCnt = 1, 73 AluCnt = 4, 74 MulCnt = 0, 75 MduCnt = 2, 76 FmacCnt = 0, 77 FmiscCnt = 0, 78 FmiscDivSqrtCnt = 0, 79 LduCnt = 2, 80 StuCnt = 2 81 ), 82 LoadPipelineWidth: Int = 2, 83 StorePipelineWidth: Int = 2, 84 StoreBufferSize: Int = 16, 85 RefillSize: Int = 512, 86 TlbEntrySize: Int = 32, 87 TlbL2EntrySize: Int = 256, // or 512 88 PtwL1EntrySize: Int = 16, 89 PtwL2EntrySize: Int = 256 90) 91 92trait HasXSParameter { 93 94 val core = Parameters.get.coreParameters 95 val env = Parameters.get.envParameters 96 97 val XLEN = core.XLEN 98 val HasMExtension = core.HasMExtension 99 val HasCExtension = core.HasCExtension 100 val HasDiv = core.HasDiv 101 val HasIcache = core.HasICache 102 val HasDcache = core.HasDCache 103 val EnableStoreQueue = core.EnableStoreQueue 104 val AddrBits = core.AddrBits // AddrBits is used in some cases 105 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 106 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 107 val AddrBytes = AddrBits / 8 // unused 108 val DataBits = XLEN 109 val DataBytes = DataBits / 8 110 val HasFPU = core.HasFPU 111 val FetchWidth = core.FectchWidth 112 val PredictWidth = FetchWidth * 2 113 val EnableBPU = core.EnableBPU 114 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 115 val EnableRAS = core.EnableRAS 116 val EnableLB = core.EnableLB 117 val EnableLoop = core.EnableLoop 118 val HistoryLength = core.HistoryLength 119 val BtbSize = core.BtbSize 120 // val BtbWays = 4 121 val BtbBanks = PredictWidth 122 // val BtbSets = BtbSize / BtbWays 123 val JbtacSize = core.JbtacSize 124 val JbtacBanks = core.JbtacBanks 125 val RasSize = core.RasSize 126 val CacheLineSize = core.CacheLineSize 127 val CacheLineHalfWord = CacheLineSize / 16 128 val ExtHistoryLength = HistoryLength + 64 129 val UBtbWays = core.UBtbWays 130 val BtbWays = core.BtbWays 131 val IBufSize = core.IBufSize 132 val DecodeWidth = core.DecodeWidth 133 val RenameWidth = core.RenameWidth 134 val CommitWidth = core.CommitWidth 135 val BrqSize = core.BrqSize 136 val IssQueSize = core.IssQueSize 137 val BrTagWidth = log2Up(BrqSize) 138 val NRPhyRegs = core.NRPhyRegs 139 val PhyRegIdxWidth = log2Up(NRPhyRegs) 140 val LsroqSize = core.LsroqSize // 64 141 val RoqSize = core.RoqSize 142 val InnerRoqIdxWidth = log2Up(RoqSize) 143 val RoqIdxWidth = InnerRoqIdxWidth + 1 144 val InnerLsroqIdxWidth = log2Up(LsroqSize) 145 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 146 val dpParams = core.dpParams 147 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 148 val exuParameters = core.exuParameters 149 val NRIntReadPorts = core.NRIntReadPorts 150 val NRIntWritePorts = core.NRIntWritePorts 151 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 152 val NRFpReadPorts = core.NRFpReadPorts 153 val NRFpWritePorts = core.NRFpWritePorts 154 val LoadPipelineWidth = core.LoadPipelineWidth 155 val StorePipelineWidth = core.StorePipelineWidth 156 val StoreBufferSize = core.StoreBufferSize 157 val RefillSize = core.RefillSize 158 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 159 val TlbEntrySize = core.TlbEntrySize 160 val TlbL2EntrySize = core.TlbL2EntrySize 161 val PtwL1EntrySize = core.PtwL1EntrySize 162 val PtwL2EntrySize = core.PtwL2EntrySize 163 164 val l1BusDataWidth = 256 165 166 val icacheParameters = ICacheParameters( 167 ) 168 169 val LRSCCycles = 100 170 val dcacheParameters = DCacheParameters( 171 tagECC = Some("secded"), 172 dataECC = Some("secded"), 173 nMissEntries = 16, 174 nLoadMissEntries = 8, 175 nStoreMissEntries = 8 176 ) 177} 178 179trait HasXSLog { this: RawModule => 180 implicit val moduleName: String = this.name 181} 182 183abstract class XSModule extends Module 184 with HasXSParameter 185 with HasExceptionNO 186 with HasXSLog 187 188//remove this trait after impl module logic 189trait NeedImpl { this: Module => 190 override protected def IO[T <: Data](iodef: T): T = { 191 val io = chisel3.experimental.IO(iodef) 192 io <> DontCare 193 io 194 } 195} 196 197abstract class XSBundle extends Bundle 198 with HasXSParameter 199 200case class EnviromentParameters 201( 202 FPGAPlatform: Boolean = true, 203 EnableDebug: Boolean = false 204) 205 206object AddressSpace extends HasXSParameter { 207 // (start, size) 208 // address out of MMIO will be considered as DRAM 209 def mmio = List( 210 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 211 (0x40000000L, 0x40000000L) // external devices 212 ) 213 214 def isMMIO(addr: UInt): Bool = mmio.map(range => { 215 require(isPow2(range._2)) 216 val bits = log2Up(range._2) 217 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 218 }).reduce(_ || _) 219} 220 221 222 223class XSCore()(implicit p: config.Parameters) extends LazyModule { 224 225 val dcache = LazyModule(new DCache()) 226 val uncache = LazyModule(new Uncache()) 227 val icache = LazyModule(new ICache()) 228 val ptw = LazyModule(new PTW()) 229 230 val mem = TLIdentityNode() 231 val mmio = uncache.clientNode 232 233 // TODO: refactor these params 234 private val l2 = LazyModule(new InclusiveCache( 235 CacheParameters( 236 level = 2, 237 ways = 4, 238 sets = 512 * 1024 / (64 * 4), 239 blockBytes = 64, 240 beatBytes = 32 // beatBytes = l1BusDataWidth / 8 241 ), 242 InclusiveCacheMicroParameters( 243 writeBytes = 8 244 ) 245 )) 246 247 private val xbar = TLXbar() 248 249 xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 250 xbar := TLBuffer() := DebugIdentityNode() := icache.clientNode 251 xbar := TLBuffer() := DebugIdentityNode() := ptw.node 252 253 l2.node := xbar 254 255 mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node 256 257 lazy val module = new XSCoreImp(this) 258} 259 260class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 261 262 val front = Module(new Frontend) 263 val backend = Module(new Backend) 264 val mem = Module(new Memend) 265 266 val dcache = outer.dcache.module 267 val uncache = outer.uncache.module 268 val icache = outer.icache.module 269 val ptw = outer.ptw.module 270 271 // TODO: connect this 272 273 front.io.backend <> backend.io.frontend 274 front.io.icacheResp <> icache.io.resp 275 front.io.icacheToTlb <> icache.io.tlb 276 icache.io.req <> front.io.icacheReq 277 icache.io.flush <> front.io.icacheFlush 278 mem.io.backend <> backend.io.mem 279 280 ptw.io.tlb(0) <> mem.io.ptw 281 ptw.io.tlb(1) <> front.io.ptw 282 283 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 284 dcache.io.lsu.lsroq <> mem.io.loadMiss 285 dcache.io.lsu.atomics <> mem.io.atomics 286 dcache.io.lsu.store <> mem.io.sbufferToDcache 287 uncache.io.lsroq <> mem.io.uncache 288 289} 290