1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 29import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 30import freechips.rocketchip.diplomacy.AddressSet 31 32case object XSCoreParamsKey extends Field[XSCoreParameters] 33 34case class XSCoreParameters 35( 36 HasPrefetch: Boolean = false, 37 HartId: Int = 0, 38 XLEN: Int = 64, 39 HasMExtension: Boolean = true, 40 HasCExtension: Boolean = true, 41 HasDiv: Boolean = true, 42 HasICache: Boolean = true, 43 HasDCache: Boolean = true, 44 AddrBits: Int = 64, 45 VAddrBits: Int = 39, 46 PAddrBits: Int = 40, 47 HasFPU: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 32, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 val ittage = Module(new ITTage()(p)) 79 // val tage = Module(new Tage()(p)) 80 // val fake = Module(new FakePredictor()(p)) 81 82 // val preds = Seq(loop, tage, btb, ubtb, bim) 83 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 84 preds.map(_.io := DontCare) 85 86 // ubtb.io.resp_in(0) := resp_in 87 // bim.io.resp_in(0) := ubtb.io.resp 88 // btb.io.resp_in(0) := bim.io.resp 89 // tage.io.resp_in(0) := btb.io.resp 90 // loop.io.resp_in(0) := tage.io.resp 91 bim.io.in.bits.resp_in(0) := resp_in 92 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 93 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 94 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 95 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 96 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 97 98 (preds, ras.io.out.resp) 99 }), 100 101 102 EnableL1plusPrefetcher: Boolean = true, 103 IBufSize: Int = 48, 104 DecodeWidth: Int = 6, 105 RenameWidth: Int = 6, 106 CommitWidth: Int = 6, 107 BrqSize: Int = 32, 108 FtqSize: Int = 64, 109 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 110 IssQueSize: Int = 16, 111 NRPhyRegs: Int = 160, 112 NRIntReadPorts: Int = 14, 113 NRIntWritePorts: Int = 8, 114 NRFpReadPorts: Int = 14, 115 NRFpWritePorts: Int = 8, 116 LoadQueueSize: Int = 64, 117 StoreQueueSize: Int = 48, 118 RoqSize: Int = 192, 119 EnableIntMoveElim: Boolean = true, 120 IntRefCounterWidth: Int = 2, 121 dpParams: DispatchParameters = DispatchParameters( 122 IntDqSize = 16, 123 FpDqSize = 16, 124 LsDqSize = 16, 125 IntDqDeqWidth = 4, 126 FpDqDeqWidth = 4, 127 LsDqDeqWidth = 4 128 ), 129 exuParameters: ExuParameters = ExuParameters( 130 JmpCnt = 1, 131 AluCnt = 4, 132 MulCnt = 0, 133 MduCnt = 2, 134 FmacCnt = 4, 135 FmiscCnt = 2, 136 FmiscDivSqrtCnt = 0, 137 LduCnt = 2, 138 StuCnt = 2 139 ), 140 LoadPipelineWidth: Int = 2, 141 StorePipelineWidth: Int = 2, 142 StoreBufferSize: Int = 16, 143 StoreBufferThreshold: Int = 7, 144 EnableFastForward: Boolean = true, 145 RefillSize: Int = 512, 146 itlbParameters: TLBParameters = TLBParameters( 147 name = "itlb", 148 fetchi = true, 149 useDmode = false, 150 sameCycle = true, 151 normalNWays = 32, 152 normalReplacer = Some("plru"), 153 superNWays = 4, 154 superReplacer = Some("plru"), 155 shouldBlock = true 156 ), 157 ldtlbParameters: TLBParameters = TLBParameters( 158 name = "ldtlb", 159 normalNSets = 128, 160 normalNWays = 1, 161 normalAssociative = "sa", 162 normalReplacer = Some("setplru"), 163 superNWays = 8, 164 normalAsVictim = true, 165 outReplace = true 166 ), 167 sttlbParameters: TLBParameters = TLBParameters( 168 name = "sttlb", 169 normalNSets = 128, 170 normalNWays = 1, 171 normalAssociative = "sa", 172 normalReplacer = Some("setplru"), 173 superNWays = 8, 174 normalAsVictim = true, 175 outReplace = true 176 ), 177 btlbParameters: TLBParameters = TLBParameters( 178 name = "btlb", 179 normalNSets = 1, 180 normalNWays = 64, 181 superNWays = 4, 182 ), 183 useBTlb: Boolean = false, 184 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 185 NumPerfCounters: Int = 16, 186 icacheParameters: ICacheParameters = ICacheParameters( 187 tagECC = Some("parity"), 188 dataECC = Some("parity"), 189 replacer = Some("setplru"), 190 nMissEntries = 2 191 ), 192 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 193 tagECC = Some("secded"), 194 dataECC = Some("secded"), 195 replacer = Some("setplru"), 196 nMissEntries = 8 197 ), 198 dcacheParameters: DCacheParameters = DCacheParameters( 199 tagECC = Some("secded"), 200 dataECC = Some("secded"), 201 replacer = Some("setplru"), 202 nMissEntries = 16, 203 nProbeEntries = 16, 204 nReleaseEntries = 16, 205 nStoreReplayEntries = 16 206 ), 207 L2Size: Int = 512 * 1024, // 512KB 208 L2NWays: Int = 8, 209 useFakePTW: Boolean = false, 210 useFakeDCache: Boolean = false, 211 useFakeL1plusCache: Boolean = false, 212 useFakeL2Cache: Boolean = false 213){ 214 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 215 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 216 217 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 218 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 219 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 220 221 val fpExuConfigs = 222 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 223 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 224 225 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 226} 227 228case object DebugOptionsKey extends Field[DebugOptions] 229 230case class DebugOptions 231( 232 FPGAPlatform: Boolean = true, 233 EnableDebug: Boolean = true, 234 EnablePerfDebug: Boolean = true, 235 UseDRAMSim: Boolean = false 236) 237 238trait HasXSParameter { 239 240 implicit val p: Parameters 241 242 val coreParams = p(XSCoreParamsKey) 243 val env = p(DebugOptionsKey) 244 245 val XLEN = coreParams.XLEN 246 val hardId = coreParams.HartId 247 val minFLen = 32 248 val fLen = 64 249 def xLen = XLEN 250 251 val HasMExtension = coreParams.HasMExtension 252 val HasCExtension = coreParams.HasCExtension 253 val HasDiv = coreParams.HasDiv 254 val HasIcache = coreParams.HasICache 255 val HasDcache = coreParams.HasDCache 256 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 257 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 258 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 259 val AddrBytes = AddrBits / 8 // unused 260 val DataBits = XLEN 261 val DataBytes = DataBits / 8 262 val HasFPU = coreParams.HasFPU 263 val FetchWidth = coreParams.FetchWidth 264 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 265 val EnableBPU = coreParams.EnableBPU 266 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 267 val EnableRAS = coreParams.EnableRAS 268 val EnableLB = coreParams.EnableLB 269 val EnableLoop = coreParams.EnableLoop 270 val EnableSC = coreParams.EnableSC 271 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 272 val HistoryLength = coreParams.HistoryLength 273 val PathHistoryLength = coreParams.PathHistoryLength 274 val BtbSize = coreParams.BtbSize 275 // val BtbWays = 4 276 val BtbBanks = PredictWidth 277 // val BtbSets = BtbSize / BtbWays 278 val JbtacSize = coreParams.JbtacSize 279 val JbtacBanks = coreParams.JbtacBanks 280 val RasSize = coreParams.RasSize 281 282 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 283 coreParams.branchPredictor(resp_in, p, enableSC) 284 } 285 286 val CacheLineSize = coreParams.CacheLineSize 287 val CacheLineHalfWord = CacheLineSize / 16 288 val ExtHistoryLength = HistoryLength + 64 289 val UBtbWays = coreParams.UBtbWays 290 val BtbWays = coreParams.BtbWays 291 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 292 val IBufSize = coreParams.IBufSize 293 val DecodeWidth = coreParams.DecodeWidth 294 val RenameWidth = coreParams.RenameWidth 295 val CommitWidth = coreParams.CommitWidth 296 val BrqSize = coreParams.BrqSize 297 val FtqSize = coreParams.FtqSize 298 val IssQueSize = coreParams.IssQueSize 299 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 300 val BrTagWidth = log2Up(BrqSize) 301 val NRPhyRegs = coreParams.NRPhyRegs 302 val PhyRegIdxWidth = log2Up(NRPhyRegs) 303 val RoqSize = coreParams.RoqSize 304 val EnableIntMoveElim = coreParams.EnableIntMoveElim 305 val IntRefCounterWidth = coreParams.IntRefCounterWidth 306 val StdFreeListSize = NRPhyRegs - 32 307 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 308 val MEFreeListSize = NRPhyRegs 309 val LoadQueueSize = coreParams.LoadQueueSize 310 val StoreQueueSize = coreParams.StoreQueueSize 311 val dpParams = coreParams.dpParams 312 val exuParameters = coreParams.exuParameters 313 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 314 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 315 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 316 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 317 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 318 val LoadPipelineWidth = coreParams.LoadPipelineWidth 319 val StorePipelineWidth = coreParams.StorePipelineWidth 320 val StoreBufferSize = coreParams.StoreBufferSize 321 val StoreBufferThreshold = coreParams.StoreBufferThreshold 322 val EnableFastForward = coreParams.EnableFastForward 323 val RefillSize = coreParams.RefillSize 324 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 325 val useBTlb = coreParams.useBTlb 326 val itlbParams = coreParams.itlbParameters 327 val ldtlbParams = coreParams.ldtlbParameters 328 val sttlbParams = coreParams.sttlbParameters 329 val btlbParams = coreParams.btlbParameters 330 val l2tlbParams = coreParams.l2tlbParameters 331 val NumPerfCounters = coreParams.NumPerfCounters 332 333 val instBytes = if (HasCExtension) 2 else 4 334 val instOffsetBits = log2Ceil(instBytes) 335 336 val icacheParameters = coreParams.icacheParameters 337 val l1plusCacheParameters = coreParams.l1plusCacheParameters 338 val dcacheParameters = coreParams.dcacheParameters 339 340 val LRSCCycles = 100 341 342 343 // cache hierarchy configurations 344 val l1BusDataWidth = 256 345 346 val useFakeDCache = coreParams.useFakeDCache 347 val useFakePTW = coreParams.useFakePTW 348 val useFakeL1plusCache = coreParams.useFakeL1plusCache 349 // L2 configurations 350 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 351 val L1BusWidth = 256 352 val L2Size = coreParams.L2Size 353 val L2BlockSize = 64 354 val L2NWays = coreParams.L2NWays 355 val L2NSets = L2Size / L2BlockSize / L2NWays 356 357 // L3 configurations 358 val L2BusWidth = 256 359 360 // icache prefetcher 361 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 362 enable = true, 363 _type = "stream", 364 streamParams = StreamPrefetchParameters( 365 streamCnt = 2, 366 streamSize = 4, 367 ageWidth = 4, 368 blockBytes = l1plusCacheParameters.blockBytes, 369 reallocStreamOnMissInstantly = true, 370 cacheName = "icache" 371 ) 372 ) 373 374 // dcache prefetcher 375 val l2PrefetcherParameters = L2PrefetcherParameters( 376 enable = true, 377 _type = "bop", // "stream" or "bop" 378 streamParams = StreamPrefetchParameters( 379 streamCnt = 4, 380 streamSize = 4, 381 ageWidth = 4, 382 blockBytes = L2BlockSize, 383 reallocStreamOnMissInstantly = true, 384 cacheName = "dcache" 385 ), 386 bopParams = BOPParameters( 387 rrTableEntries = 256, 388 rrTagBits = 12, 389 scoreBits = 5, 390 roundMax = 50, 391 badScore = 1, 392 blockBytes = L2BlockSize, 393 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 394 ), 395 ) 396 397 // load violation predict 398 val ResetTimeMax2Pow = 20 //1078576 399 val ResetTimeMin2Pow = 10 //1024 400 // wait table parameters 401 val WaitTableSize = 1024 402 val MemPredPCWidth = log2Up(WaitTableSize) 403 val LWTUse2BitCounter = true 404 // store set parameters 405 val SSITSize = WaitTableSize 406 val LFSTSize = 32 407 val SSIDWidth = log2Up(LFSTSize) 408 val LFSTWidth = 4 409 val StoreSetEnable = true // LWT will be disabled if SS is enabled 410 411 val loadExuConfigs = coreParams.loadExuConfigs 412 val storeExuConfigs = coreParams.storeExuConfigs 413 414 val intExuConfigs = coreParams.intExuConfigs 415 416 val fpExuConfigs = coreParams.fpExuConfigs 417 418 val exuConfigs = coreParams.exuConfigs 419 420} 421