1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import freechips.rocketchip.tile.MaxHartIdBits 31import system.SoCParamsKey 32import huancun._ 33import huancun.debug._ 34import xiangshan.cache.wpu.WPUParameters 35import coupledL2._ 36import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 37 38import scala.math.min 39 40case object XSTileKey extends Field[Seq[XSCoreParameters]] 41 42case object XSCoreParamsKey extends Field[XSCoreParameters] 43 44case class XSCoreParameters 45( 46 HasPrefetch: Boolean = false, 47 HartId: Int = 0, 48 XLEN: Int = 64, 49 VLEN: Int = 128, 50 HSXLEN: Int = 64, 51 HasMExtension: Boolean = true, 52 HasCExtension: Boolean = true, 53 HasHExtension: Boolean = true, 54 HasDiv: Boolean = true, 55 HasICache: Boolean = true, 56 HasDCache: Boolean = true, 57 AddrBits: Int = 64, 58 VAddrBits: Int = 39, 59 GPAddrBits: Int = 41, 60 HasFPU: Boolean = true, 61 HasCustomCSRCacheOp: Boolean = true, 62 FetchWidth: Int = 8, 63 AsidLength: Int = 16, 64 VmidLength: Int = 14, 65 EnableBPU: Boolean = true, 66 EnableBPD: Boolean = true, 67 EnableRAS: Boolean = true, 68 EnableLB: Boolean = false, 69 EnableLoop: Boolean = true, 70 EnableSC: Boolean = true, 71 EnbaleTlbDebug: Boolean = false, 72 EnableJal: Boolean = false, 73 EnableFauFTB: Boolean = true, 74 UbtbGHRLength: Int = 4, 75 // HistoryLength: Int = 512, 76 EnableGHistDiff: Boolean = true, 77 EnableCommitGHistDiff: Boolean = true, 78 UbtbSize: Int = 256, 79 FtbSize: Int = 2048, 80 RasSize: Int = 16, 81 RasSpecSize: Int = 32, 82 RasCtrSize: Int = 3, 83 CacheLineSize: Int = 512, 84 FtbWays: Int = 4, 85 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 86 // Sets Hist Tag 87 // Seq(( 2048, 2, 8), 88 // ( 2048, 9, 8), 89 // ( 2048, 13, 8), 90 // ( 2048, 20, 8), 91 // ( 2048, 26, 8), 92 // ( 2048, 44, 8), 93 // ( 2048, 73, 8), 94 // ( 2048, 256, 8)), 95 Seq(( 4096, 8, 8), 96 ( 4096, 13, 8), 97 ( 4096, 32, 8), 98 ( 4096, 119, 8)), 99 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 100 // Sets Hist Tag 101 Seq(( 256, 4, 9), 102 ( 256, 8, 9), 103 ( 512, 13, 9), 104 ( 512, 16, 9), 105 ( 512, 32, 9)), 106 SCNRows: Int = 512, 107 SCNTables: Int = 4, 108 SCCtrBits: Int = 6, 109 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 110 numBr: Int = 2, 111 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 112 ((resp_in: BranchPredictionResp, p: Parameters) => { 113 val ftb = Module(new FTB()(p)) 114 val ubtb =Module(new FauFTB()(p)) 115 // val bim = Module(new BIM()(p)) 116 val tage = Module(new Tage_SC()(p)) 117 val ras = Module(new RAS()(p)) 118 val ittage = Module(new ITTage()(p)) 119 val preds = Seq(ubtb, tage, ftb, ittage, ras) 120 preds.map(_.io := DontCare) 121 122 // ubtb.io.resp_in(0) := resp_in 123 // bim.io.resp_in(0) := ubtb.io.resp 124 // btb.io.resp_in(0) := bim.io.resp 125 // tage.io.resp_in(0) := btb.io.resp 126 // loop.io.resp_in(0) := tage.io.resp 127 ubtb.io.in.bits.resp_in(0) := resp_in 128 tage.io.in.bits.resp_in(0) := ubtb.io.out 129 ftb.io.in.bits.resp_in(0) := tage.io.out 130 ittage.io.in.bits.resp_in(0) := ftb.io.out 131 ras.io.in.bits.resp_in(0) := ittage.io.out 132 133 (preds, ras.io.out) 134 }), 135 ICacheECCForceError: Boolean = false, 136 IBufSize: Int = 48, 137 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 138 DecodeWidth: Int = 6, 139 RenameWidth: Int = 6, 140 CommitWidth: Int = 6, 141 EnableRenameSnapshot: Boolean = true, 142 RenameSnapshotNum: Int = 4, 143 FtqSize: Int = 64, 144 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 145 IssQueSize: Int = 16, 146 NRPhyRegs: Int = 192, 147 VirtualLoadQueueSize: Int = 80, 148 LoadQueueRARSize: Int = 80, 149 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 150 RollbackGroupSize: Int = 8, 151 LoadQueueReplaySize: Int = 72, 152 LoadUncacheBufferSize: Int = 20, 153 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 154 StoreQueueSize: Int = 64, 155 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 156 StoreQueueForwardWithMask: Boolean = true, 157 VlsQueueSize: Int = 8, 158 RobSize: Int = 256, 159 dpParams: DispatchParameters = DispatchParameters( 160 IntDqSize = 16, 161 FpDqSize = 16, 162 LsDqSize = 16, 163 IntDqDeqWidth = 4, 164 FpDqDeqWidth = 4, 165 LsDqDeqWidth = 4 166 ), 167 exuParameters: ExuParameters = ExuParameters( 168 JmpCnt = 1, 169 AluCnt = 4, 170 MulCnt = 0, 171 MduCnt = 2, 172 FmacCnt = 4, 173 FmiscCnt = 2, 174 FmiscDivSqrtCnt = 0, 175 LduCnt = 2, 176 StuCnt = 2 177 ), 178 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 179 LoadPipelineWidth: Int = 2, 180 StorePipelineWidth: Int = 2, 181 VecMemSrcInWidth: Int = 2, 182 VecMemInstWbWidth: Int = 1, 183 VecMemDispatchWidth: Int = 1, 184 StoreBufferSize: Int = 16, 185 StoreBufferThreshold: Int = 7, 186 EnsbufferWidth: Int = 2, 187 UncacheBufferSize: Int = 4, 188 EnableLoadToLoadForward: Boolean = false, 189 EnableFastForward: Boolean = true, 190 EnableLdVioCheckAfterReset: Boolean = true, 191 EnableSoftPrefetchAfterReset: Boolean = true, 192 EnableCacheErrorAfterReset: Boolean = true, 193 EnableAccurateLoadError: Boolean = true, 194 EnableUncacheWriteOutstanding: Boolean = false, 195 EnableStorePrefetchAtIssue: Boolean = false, 196 EnableStorePrefetchAtCommit: Boolean = false, 197 EnableAtCommitMissTrigger: Boolean = true, 198 EnableStorePrefetchSMS: Boolean = false, 199 EnableStorePrefetchSPB: Boolean = false, 200 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 201 MMUVmidLen: Int = 14, 202 ReSelectLen: Int = 7, // load replay queue replay select counter len 203 iwpuParameters: WPUParameters = WPUParameters( 204 enWPU = false, 205 algoName = "mmru", 206 isICache = true, 207 ), 208 dwpuParameters: WPUParameters = WPUParameters( 209 enWPU = false, 210 algoName = "mmru", 211 enCfPred = false, 212 isICache = false, 213 ), 214 itlbParameters: TLBParameters = TLBParameters( 215 name = "itlb", 216 fetchi = true, 217 useDmode = false, 218 NWays = 48, 219 ), 220 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 221 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 222 ldtlbParameters: TLBParameters = TLBParameters( 223 name = "ldtlb", 224 NWays = 48, 225 outReplace = false, 226 partialStaticPMP = true, 227 outsideRecvFlush = true, 228 saveLevel = true 229 ), 230 sttlbParameters: TLBParameters = TLBParameters( 231 name = "sttlb", 232 NWays = 48, 233 outReplace = false, 234 partialStaticPMP = true, 235 outsideRecvFlush = true, 236 saveLevel = true 237 ), 238 pftlbParameters: TLBParameters = TLBParameters( 239 name = "pftlb", 240 NWays = 48, 241 outReplace = false, 242 partialStaticPMP = true, 243 outsideRecvFlush = true, 244 saveLevel = true 245 ), 246 refillBothTlb: Boolean = false, 247 btlbParameters: TLBParameters = TLBParameters( 248 name = "btlb", 249 NWays = 48, 250 ), 251 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 252 NumPerfCounters: Int = 16, 253 icacheParameters: ICacheParameters = ICacheParameters( 254 tagECC = Some("parity"), 255 dataECC = Some("parity"), 256 replacer = Some("setplru"), 257 nMissEntries = 2, 258 nProbeEntries = 2, 259 nPrefetchEntries = 12, 260 nPrefBufferEntries = 32, 261 ), 262 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 263 tagECC = Some("secded"), 264 dataECC = Some("secded"), 265 replacer = Some("setplru"), 266 nMissEntries = 16, 267 nProbeEntries = 8, 268 nReleaseEntries = 18, 269 nMaxPrefetchEntry = 6, 270 )), 271 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 272 name = "l2", 273 ways = 8, 274 sets = 1024, // default 512KB L2 275 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 276 )), 277 L2NBanks: Int = 1, 278 usePTWRepeater: Boolean = false, 279 softTLB: Boolean = false, // dpi-c l1tlb debug only 280 softPTW: Boolean = false, // dpi-c l2tlb debug only 281 softPTWDelay: Int = 1 282){ 283 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 284 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 285 286 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 287 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 288 289 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 290 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 291 292 val fpExuConfigs = 293 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 294 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 295 296 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 297} 298 299case object DebugOptionsKey extends Field[DebugOptions] 300 301case class DebugOptions 302( 303 FPGAPlatform: Boolean = false, 304 EnableDifftest: Boolean = false, 305 AlwaysBasicDiff: Boolean = true, 306 EnableDebug: Boolean = false, 307 EnablePerfDebug: Boolean = true, 308 UseDRAMSim: Boolean = false, 309 EnableConstantin: Boolean = false, 310 EnableChiselDB: Boolean = false, 311 AlwaysBasicDB: Boolean = true, 312 EnableRollingDB: Boolean = false 313) 314 315trait HasXSParameter { 316 317 implicit val p: Parameters 318 319 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 320 321 val coreParams = p(XSCoreParamsKey) 322 val env = p(DebugOptionsKey) 323 324 val XLEN = coreParams.XLEN 325 val VLEN = coreParams.VLEN 326 val HSXLEN = coreParams.HSXLEN 327 val minFLen = 32 328 val fLen = 64 329 val hartIdLen = p(MaxHartIdBits) 330 def xLen = XLEN 331 332 val HasMExtension = coreParams.HasMExtension 333 val HasCExtension = coreParams.HasCExtension 334 val HasHExtension = coreParams.HasHExtension 335 val HasDiv = coreParams.HasDiv 336 val HasIcache = coreParams.HasICache 337 val HasDcache = coreParams.HasDCache 338 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 339 val GPAddrBits = coreParams.GPAddrBits 340 val VAddrBits = { 341 if(HasHExtension){ 342 coreParams.GPAddrBits 343 }else{ 344 coreParams.VAddrBits 345 } 346 } // VAddrBits is Virtual Memory addr bits 347 348 val AsidLength = coreParams.AsidLength 349 val VmidLength = coreParams.VmidLength 350 val ReSelectLen = coreParams.ReSelectLen 351 val AddrBytes = AddrBits / 8 // unused 352 val DataBits = XLEN 353 val DataBytes = DataBits / 8 354 val VDataBytes = VLEN / 8 355 val HasFPU = coreParams.HasFPU 356 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 357 val FetchWidth = coreParams.FetchWidth 358 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 359 val EnableBPU = coreParams.EnableBPU 360 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 361 val EnableRAS = coreParams.EnableRAS 362 val EnableLB = coreParams.EnableLB 363 val EnableLoop = coreParams.EnableLoop 364 val EnableSC = coreParams.EnableSC 365 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 366 val HistoryLength = coreParams.HistoryLength 367 val EnableGHistDiff = coreParams.EnableGHistDiff 368 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 369 val UbtbGHRLength = coreParams.UbtbGHRLength 370 val UbtbSize = coreParams.UbtbSize 371 val EnableFauFTB = coreParams.EnableFauFTB 372 val FtbSize = coreParams.FtbSize 373 val FtbWays = coreParams.FtbWays 374 val RasSize = coreParams.RasSize 375 val RasSpecSize = coreParams.RasSpecSize 376 val RasCtrSize = coreParams.RasCtrSize 377 378 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 379 coreParams.branchPredictor(resp_in, p) 380 } 381 val numBr = coreParams.numBr 382 val TageTableInfos = coreParams.TageTableInfos 383 val TageBanks = coreParams.numBr 384 val SCNRows = coreParams.SCNRows 385 val SCCtrBits = coreParams.SCCtrBits 386 val SCHistLens = coreParams.SCHistLens 387 val SCNTables = coreParams.SCNTables 388 389 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 390 case ((n, cb), h) => (n, cb, h) 391 } 392 val ITTageTableInfos = coreParams.ITTageTableInfos 393 type FoldedHistoryInfo = Tuple2[Int, Int] 394 val foldedGHistInfos = 395 (TageTableInfos.map{ case (nRows, h, t) => 396 if (h > 0) 397 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 398 else 399 Set[FoldedHistoryInfo]() 400 }.reduce(_++_).toSet ++ 401 SCTableInfos.map{ case (nRows, _, h) => 402 if (h > 0) 403 Set((h, min(log2Ceil(nRows/TageBanks), h))) 404 else 405 Set[FoldedHistoryInfo]() 406 }.reduce(_++_).toSet ++ 407 ITTageTableInfos.map{ case (nRows, h, t) => 408 if (h > 0) 409 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 410 else 411 Set[FoldedHistoryInfo]() 412 }.reduce(_++_) ++ 413 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 414 ).toList 415 416 417 418 val CacheLineSize = coreParams.CacheLineSize 419 val CacheLineHalfWord = CacheLineSize / 16 420 val ExtHistoryLength = HistoryLength + 64 421 val ICacheECCForceError = coreParams.ICacheECCForceError 422 val IBufSize = coreParams.IBufSize 423 val IBufNBank = coreParams.IBufNBank 424 val DecodeWidth = coreParams.DecodeWidth 425 val RenameWidth = coreParams.RenameWidth 426 val CommitWidth = coreParams.CommitWidth 427 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 428 val RenameSnapshotNum = coreParams.RenameSnapshotNum 429 val FtqSize = coreParams.FtqSize 430 val IssQueSize = coreParams.IssQueSize 431 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 432 val NRPhyRegs = coreParams.NRPhyRegs 433 val PhyRegIdxWidth = log2Up(NRPhyRegs) 434 val RobSize = coreParams.RobSize 435 val IntRefCounterWidth = log2Ceil(RobSize) 436 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 437 val LoadQueueRARSize = coreParams.LoadQueueRARSize 438 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 439 val RollbackGroupSize = coreParams.RollbackGroupSize 440 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 441 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 442 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 443 val StoreQueueSize = coreParams.StoreQueueSize 444 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 445 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 446 val VlsQueueSize = coreParams.VlsQueueSize 447 val dpParams = coreParams.dpParams 448 val exuParameters = coreParams.exuParameters 449 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 450 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 451 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 452 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 453 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 454 val NumRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 455 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 456 val FtqRedirectAheadNum = exuParameters.AluCnt 457 val LoadPipelineWidth = coreParams.LoadPipelineWidth 458 val StorePipelineWidth = coreParams.StorePipelineWidth 459 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 460 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 461 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 462 val StoreBufferSize = coreParams.StoreBufferSize 463 val StoreBufferThreshold = coreParams.StoreBufferThreshold 464 val EnsbufferWidth = coreParams.EnsbufferWidth 465 val UncacheBufferSize = coreParams.UncacheBufferSize 466 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 467 val EnableFastForward = coreParams.EnableFastForward 468 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 469 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 470 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 471 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 472 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 473 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 474 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 475 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 476 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 477 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 478 require(LoadPipelineWidth == StorePipelineWidth, "LoadPipelineWidth must be equal StorePipelineWidth!") 479 require(LoadPipelineWidth == exuParameters.LduCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 480 require(StorePipelineWidth == exuParameters.StuCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 481 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 482 val asidLen = coreParams.MMUAsidLen 483 val vmidLen = coreParams.MMUVmidLen 484 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 485 val refillBothTlb = coreParams.refillBothTlb 486 val iwpuParam = coreParams.iwpuParameters 487 val dwpuParam = coreParams.dwpuParameters 488 val itlbParams = coreParams.itlbParameters 489 val ldtlbParams = coreParams.ldtlbParameters 490 val sttlbParams = coreParams.sttlbParameters 491 val pftlbParams = coreParams.pftlbParameters 492 val btlbParams = coreParams.btlbParameters 493 val l2tlbParams = coreParams.l2tlbParameters 494 val NumPerfCounters = coreParams.NumPerfCounters 495 496 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 497 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 498 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 499 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 500 501 val instBytes = if (HasCExtension) 2 else 4 502 val instOffsetBits = log2Ceil(instBytes) 503 504 val icacheParameters = coreParams.icacheParameters 505 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 506 507 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 508 // for constrained LR/SC loop 509 val LRSCCycles = 64 510 // for lr storm 511 val LRSCBackOff = 8 512 513 // cache hierarchy configurations 514 val l1BusDataWidth = 256 515 516 // load violation predict 517 val ResetTimeMax2Pow = 20 //1078576 518 val ResetTimeMin2Pow = 10 //1024 519 // wait table parameters 520 val WaitTableSize = 1024 521 val MemPredPCWidth = log2Up(WaitTableSize) 522 val LWTUse2BitCounter = true 523 // store set parameters 524 val SSITSize = WaitTableSize 525 val LFSTSize = 32 526 val SSIDWidth = log2Up(LFSTSize) 527 val LFSTWidth = 4 528 val StoreSetEnable = true // LWT will be disabled if SS is enabled 529 val LFSTEnable = false 530 val loadExuConfigs = coreParams.loadExuConfigs 531 val storeExuConfigs = coreParams.storeExuConfigs 532 533 val intExuConfigs = coreParams.intExuConfigs 534 535 val fpExuConfigs = coreParams.fpExuConfigs 536 537 val exuConfigs = coreParams.exuConfigs 538 539 val PCntIncrStep: Int = 6 540 val numPCntHc: Int = 25 541 val numPCntPtw: Int = 19 542 543 val numCSRPCntFrontend = 8 544 val numCSRPCntCtrl = 8 545 val numCSRPCntLsu = 8 546 val numCSRPCntHc = 5 547 val printEventCoding = true 548} 549