1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import scala.math.min 32 33case object XSTileKey extends Field[Seq[XSCoreParameters]] 34 35case object XSCoreParamsKey extends Field[XSCoreParameters] 36 37case class XSCoreParameters 38( 39 HasPrefetch: Boolean = false, 40 HartId: Int = 0, 41 XLEN: Int = 64, 42 HasMExtension: Boolean = true, 43 HasCExtension: Boolean = true, 44 HasDiv: Boolean = true, 45 HasICache: Boolean = true, 46 HasDCache: Boolean = true, 47 AddrBits: Int = 64, 48 VAddrBits: Int = 39, 49 HasFPU: Boolean = true, 50 HasCustomCSRCacheOp: Boolean = true, 51 FetchWidth: Int = 8, 52 AsidLength: Int = 16, 53 EnableBPU: Boolean = true, 54 EnableBPD: Boolean = true, 55 EnableRAS: Boolean = true, 56 EnableLB: Boolean = false, 57 EnableLoop: Boolean = true, 58 EnableSC: Boolean = true, 59 EnbaleTlbDebug: Boolean = false, 60 EnableJal: Boolean = false, 61 EnableUBTB: Boolean = true, 62 HistoryLength: Int = 256, 63 PathHistoryLength: Int = 16, 64 BtbSize: Int = 2048, 65 JbtacSize: Int = 1024, 66 JbtacBanks: Int = 8, 67 RasSize: Int = 32, 68 CacheLineSize: Int = 512, 69 UBtbWays: Int = 16, 70 BtbWays: Int = 2, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 128*8, 2, 7), 74 ( 128*8, 4, 7), 75 ( 256*8, 8, 8), 76 ( 256*8, 16, 8), 77 ( 128*8, 32, 9), 78 ( 128*8, 65, 9)), 79 TageBanks: Int = 2, 80 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 81 // Sets Hist Tag 82 Seq(( 512, 0, 0), 83 ( 256, 4, 8), 84 ( 256, 8, 8), 85 ( 512, 12, 8), 86 ( 512, 16, 8), 87 ( 512, 32, 8)), 88 SCNRows: Int = 1024, 89 SCNTables: Int = 6, 90 SCCtrBits: Int = 6, 91 numBr: Int = 2, 92 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 93 ((resp_in: BranchPredictionResp, p: Parameters) => { 94 // val loop = Module(new LoopPredictor) 95 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 96 // else Module(new Tage) } 97 // else { Module(new FakeTage) }) 98 val ftb = Module(new FTB()(p)) 99 val ubtb = Module(new MicroBTB()(p)) 100 val bim = Module(new BIM()(p)) 101 val tage = Module(new Tage_SC()(p)) 102 val ras = Module(new RAS()(p)) 103 val ittage = Module(new ITTage()(p)) 104 // val tage = Module(new Tage()(p)) 105 // val fake = Module(new FakePredictor()(p)) 106 107 // val preds = Seq(loop, tage, btb, ubtb, bim) 108 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 bim.io.in.bits.resp_in(0) := resp_in 117 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 118 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 119 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 120 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 121 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 122 123 (preds, ras.io.out.resp) 124 }), 125 IBufSize: Int = 48, 126 DecodeWidth: Int = 6, 127 RenameWidth: Int = 6, 128 CommitWidth: Int = 6, 129 FtqSize: Int = 64, 130 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 131 IssQueSize: Int = 16, 132 NRPhyRegs: Int = 192, 133 NRIntReadPorts: Int = 14, 134 NRIntWritePorts: Int = 8, 135 NRFpReadPorts: Int = 14, 136 NRFpWritePorts: Int = 8, 137 LoadQueueSize: Int = 80, 138 StoreQueueSize: Int = 64, 139 RobSize: Int = 256, 140 dpParams: DispatchParameters = DispatchParameters( 141 IntDqSize = 16, 142 FpDqSize = 16, 143 LsDqSize = 16, 144 IntDqDeqWidth = 4, 145 FpDqDeqWidth = 4, 146 LsDqDeqWidth = 4 147 ), 148 exuParameters: ExuParameters = ExuParameters( 149 JmpCnt = 1, 150 AluCnt = 4, 151 MulCnt = 0, 152 MduCnt = 2, 153 FmacCnt = 4, 154 FmiscCnt = 2, 155 FmiscDivSqrtCnt = 0, 156 LduCnt = 2, 157 StuCnt = 2 158 ), 159 LoadPipelineWidth: Int = 2, 160 StorePipelineWidth: Int = 2, 161 StoreBufferSize: Int = 16, 162 StoreBufferThreshold: Int = 7, 163 EnableFastForward: Boolean = true, 164 EnableLdVioCheckAfterReset: Boolean = true, 165 RefillSize: Int = 512, 166 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 167 itlbParameters: TLBParameters = TLBParameters( 168 name = "itlb", 169 fetchi = true, 170 useDmode = false, 171 sameCycle = true, 172 normalNWays = 32, 173 normalReplacer = Some("plru"), 174 superNWays = 4, 175 superReplacer = Some("plru"), 176 shouldBlock = true 177 ), 178 ldtlbParameters: TLBParameters = TLBParameters( 179 name = "ldtlb", 180 normalNSets = 128, 181 normalNWays = 1, 182 normalAssociative = "sa", 183 normalReplacer = Some("setplru"), 184 superNWays = 8, 185 normalAsVictim = true, 186 outReplace = true 187 ), 188 sttlbParameters: TLBParameters = TLBParameters( 189 name = "sttlb", 190 normalNSets = 128, 191 normalNWays = 1, 192 normalAssociative = "sa", 193 normalReplacer = Some("setplru"), 194 superNWays = 8, 195 normalAsVictim = true, 196 outReplace = true 197 ), 198 refillBothTlb: Boolean = false, 199 btlbParameters: TLBParameters = TLBParameters( 200 name = "btlb", 201 normalNSets = 1, 202 normalNWays = 64, 203 superNWays = 4, 204 ), 205 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 206 NumPMP: Int = 16, // 0 or 16 or 64 207 NumPMA: Int = 16, 208 NumPerfCounters: Int = 16, 209 icacheParameters: ICacheParameters = ICacheParameters( 210 tagECC = Some("parity"), 211 dataECC = Some("parity"), 212 replacer = Some("setplru"), 213 nMissEntries = 2 214 ), 215 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 216 tagECC = Some("secded"), 217 dataECC = Some("secded"), 218 replacer = Some("setplru"), 219 nMissEntries = 16, 220 nProbeEntries = 8, 221 nReleaseEntries = 18 222 )), 223 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 224 name = "l2", 225 level = 2, 226 ways = 8, 227 sets = 1024, // default 512KB L2 228 prefetch = Some(huancun.prefetch.BOPParameters()) 229 )), 230 L2NBanks: Int = 1, 231 usePTWRepeater: Boolean = false, 232 softPTW: Boolean = false // dpi-c debug only 233){ 234 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 235 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 236 237 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 238 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 239 240 val fpExuConfigs = 241 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 242 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 243 244 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 245} 246 247case object DebugOptionsKey extends Field[DebugOptions] 248 249case class DebugOptions 250( 251 FPGAPlatform: Boolean = true, 252 EnableDebug: Boolean = true, 253 EnablePerfDebug: Boolean = true, 254 UseDRAMSim: Boolean = false 255) 256 257trait HasXSParameter { 258 259 implicit val p: Parameters 260 261 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 262 263 val coreParams = p(XSCoreParamsKey) 264 val env = p(DebugOptionsKey) 265 266 val XLEN = coreParams.XLEN 267 val hardId = coreParams.HartId 268 val minFLen = 32 269 val fLen = 64 270 def xLen = XLEN 271 272 val HasMExtension = coreParams.HasMExtension 273 val HasCExtension = coreParams.HasCExtension 274 val HasDiv = coreParams.HasDiv 275 val HasIcache = coreParams.HasICache 276 val HasDcache = coreParams.HasDCache 277 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 278 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 279 val AsidLength = coreParams.AsidLength 280 val AddrBytes = AddrBits / 8 // unused 281 val DataBits = XLEN 282 val DataBytes = DataBits / 8 283 val HasFPU = coreParams.HasFPU 284 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 285 val FetchWidth = coreParams.FetchWidth 286 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 287 val EnableBPU = coreParams.EnableBPU 288 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 289 val EnableRAS = coreParams.EnableRAS 290 val EnableLB = coreParams.EnableLB 291 val EnableLoop = coreParams.EnableLoop 292 val EnableSC = coreParams.EnableSC 293 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 294 val HistoryLength = coreParams.HistoryLength 295 val PathHistoryLength = coreParams.PathHistoryLength 296 val BtbSize = coreParams.BtbSize 297 // val BtbWays = 4 298 val BtbBanks = PredictWidth 299 // val BtbSets = BtbSize / BtbWays 300 val JbtacSize = coreParams.JbtacSize 301 val JbtacBanks = coreParams.JbtacBanks 302 val RasSize = coreParams.RasSize 303 304 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 305 coreParams.branchPredictor(resp_in, p) 306 } 307 val numBr = coreParams.numBr 308 val TageTableInfos = coreParams.TageTableInfos 309 310 311 val BankTageTableInfos = (0 until numBr).map(i => 312 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 313 ) 314 val TageBanks = coreParams.TageBanks 315 val SCNRows = coreParams.SCNRows 316 val SCCtrBits = coreParams.SCCtrBits 317 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 318 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 319 320 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 321 case (ntable, histlens) => 322 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 323 } 324 val ITTageTableInfos = coreParams.ITTageTableInfos 325 type FoldedHistoryInfo = Tuple2[Int, Int] 326 val foldedGHistInfos = 327 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 328 if (h > 0) 329 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 330 else 331 Set[FoldedHistoryInfo]() 332 }.reduce(_++_)).toSet ++ 333 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 334 if (h > 0) 335 Set((h, min(log2Ceil(nRows/TageBanks), h))) 336 else 337 Set[FoldedHistoryInfo]() 338 }.reduce(_++_)).toSet ++ 339 ITTageTableInfos.map{ case (nRows, h, t) => 340 if (h > 0) 341 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 342 else 343 Set[FoldedHistoryInfo]() 344 }.reduce(_++_)).toList 345 346 val CacheLineSize = coreParams.CacheLineSize 347 val CacheLineHalfWord = CacheLineSize / 16 348 val ExtHistoryLength = HistoryLength + 64 349 val UBtbWays = coreParams.UBtbWays 350 val BtbWays = coreParams.BtbWays 351 val IBufSize = coreParams.IBufSize 352 val DecodeWidth = coreParams.DecodeWidth 353 val RenameWidth = coreParams.RenameWidth 354 val CommitWidth = coreParams.CommitWidth 355 val FtqSize = coreParams.FtqSize 356 val IssQueSize = coreParams.IssQueSize 357 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 358 val NRPhyRegs = coreParams.NRPhyRegs 359 val PhyRegIdxWidth = log2Up(NRPhyRegs) 360 val RobSize = coreParams.RobSize 361 val IntRefCounterWidth = log2Ceil(RobSize) 362 val StdFreeListSize = NRPhyRegs - 32 363 val MEFreeListSize = NRPhyRegs 364 val LoadQueueSize = coreParams.LoadQueueSize 365 val StoreQueueSize = coreParams.StoreQueueSize 366 val dpParams = coreParams.dpParams 367 val exuParameters = coreParams.exuParameters 368 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 369 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 370 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 371 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 372 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 373 val LoadPipelineWidth = coreParams.LoadPipelineWidth 374 val StorePipelineWidth = coreParams.StorePipelineWidth 375 val StoreBufferSize = coreParams.StoreBufferSize 376 val StoreBufferThreshold = coreParams.StoreBufferThreshold 377 val EnableFastForward = coreParams.EnableFastForward 378 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 379 val RefillSize = coreParams.RefillSize 380 val asidLen = coreParams.MMUAsidLen 381 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 382 val refillBothTlb = coreParams.refillBothTlb 383 val itlbParams = coreParams.itlbParameters 384 val ldtlbParams = coreParams.ldtlbParameters 385 val sttlbParams = coreParams.sttlbParameters 386 val btlbParams = coreParams.btlbParameters 387 val l2tlbParams = coreParams.l2tlbParameters 388 val NumPMP = coreParams.NumPMP 389 val NumPMA = coreParams.NumPMA 390 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 391 val NumPerfCounters = coreParams.NumPerfCounters 392 393 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 394 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 395 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 396 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 397 398 val instBytes = if (HasCExtension) 2 else 4 399 val instOffsetBits = log2Ceil(instBytes) 400 401 val icacheParameters = coreParams.icacheParameters 402 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 403 404 val LRSCCycles = 100 405 406 // cache hierarchy configurations 407 val l1BusDataWidth = 256 408 409 // load violation predict 410 val ResetTimeMax2Pow = 20 //1078576 411 val ResetTimeMin2Pow = 10 //1024 412 // wait table parameters 413 val WaitTableSize = 1024 414 val MemPredPCWidth = log2Up(WaitTableSize) 415 val LWTUse2BitCounter = true 416 // store set parameters 417 val SSITSize = WaitTableSize 418 val LFSTSize = 32 419 val SSIDWidth = log2Up(LFSTSize) 420 val LFSTWidth = 4 421 val StoreSetEnable = true // LWT will be disabled if SS is enabled 422 423 val loadExuConfigs = coreParams.loadExuConfigs 424 val storeExuConfigs = coreParams.storeExuConfigs 425 426 val intExuConfigs = coreParams.intExuConfigs 427 428 val fpExuConfigs = coreParams.fpExuConfigs 429 430 val exuConfigs = coreParams.exuConfigs 431 432 val PCntIncrStep: Int = 6 433 val numPCntHc: Int = 25 434 val numPCntPtw: Int = 19 435 436 val numCSRPCntFrontend = 8 437 val numCSRPCntCtrl = 8 438 val numCSRPCntLsu = 8 439 val numCSRPCntHc = 5 440 val print_perfcounter = false 441} 442