1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import scala.math.min 32 33case object XSTileKey extends Field[Seq[XSCoreParameters]] 34 35case object XSCoreParamsKey extends Field[XSCoreParameters] 36 37case class XSCoreParameters 38( 39 HasPrefetch: Boolean = false, 40 HartId: Int = 0, 41 XLEN: Int = 64, 42 HasMExtension: Boolean = true, 43 HasCExtension: Boolean = true, 44 HasDiv: Boolean = true, 45 HasICache: Boolean = true, 46 HasDCache: Boolean = true, 47 AddrBits: Int = 64, 48 VAddrBits: Int = 39, 49 HasFPU: Boolean = true, 50 HasCustomCSRCacheOp: Boolean = true, 51 FetchWidth: Int = 8, 52 AsidLength: Int = 16, 53 EnableBPU: Boolean = true, 54 EnableBPD: Boolean = true, 55 EnableRAS: Boolean = true, 56 EnableLB: Boolean = false, 57 EnableLoop: Boolean = true, 58 EnableSC: Boolean = true, 59 EnbaleTlbDebug: Boolean = false, 60 EnableJal: Boolean = false, 61 EnableUBTB: Boolean = true, 62 HistoryLength: Int = 128, 63 PathHistoryLength: Int = 16, 64 BtbSize: Int = 2048, 65 JbtacSize: Int = 1024, 66 JbtacBanks: Int = 8, 67 RasSize: Int = 32, 68 CacheLineSize: Int = 512, 69 UBtbWays: Int = 16, 70 BtbWays: Int = 2, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 128*8, 2, 7), 74 ( 128*8, 4, 7), 75 ( 256*8, 8, 8), 76 ( 256*8, 16, 8), 77 ( 128*8, 32, 9), 78 ( 128*8, 65, 9)), 79 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 80 // Sets Hist Tag 81 Seq(( 512, 0, 0), 82 ( 256, 4, 8), 83 ( 256, 8, 8), 84 ( 512, 12, 8), 85 ( 512, 16, 8), 86 ( 512, 32, 8)), 87 SCNRows: Int = 1024, 88 SCNTables: Int = 6, 89 SCCtrBits: Int = 6, 90 numBr: Int = 2, 91 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 92 ((resp_in: BranchPredictionResp, p: Parameters) => { 93 // val loop = Module(new LoopPredictor) 94 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 95 // else Module(new Tage) } 96 // else { Module(new FakeTage) }) 97 val ftb = Module(new FTB()(p)) 98 val ubtb = Module(new MicroBTB()(p)) 99 val bim = Module(new BIM()(p)) 100 val tage = Module(new Tage_SC()(p)) 101 val ras = Module(new RAS()(p)) 102 val ittage = Module(new ITTage()(p)) 103 // val tage = Module(new Tage()(p)) 104 // val fake = Module(new FakePredictor()(p)) 105 106 // val preds = Seq(loop, tage, btb, ubtb, bim) 107 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 108 preds.map(_.io := DontCare) 109 110 // ubtb.io.resp_in(0) := resp_in 111 // bim.io.resp_in(0) := ubtb.io.resp 112 // btb.io.resp_in(0) := bim.io.resp 113 // tage.io.resp_in(0) := btb.io.resp 114 // loop.io.resp_in(0) := tage.io.resp 115 bim.io.in.bits.resp_in(0) := resp_in 116 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 117 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 118 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 119 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 120 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 121 122 (preds, ras.io.out.resp) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 NRIntReadPorts: Int = 14, 133 NRIntWritePorts: Int = 8, 134 NRFpReadPorts: Int = 14, 135 NRFpWritePorts: Int = 8, 136 LoadQueueSize: Int = 80, 137 StoreQueueSize: Int = 64, 138 RobSize: Int = 256, 139 dpParams: DispatchParameters = DispatchParameters( 140 IntDqSize = 16, 141 FpDqSize = 16, 142 LsDqSize = 16, 143 IntDqDeqWidth = 4, 144 FpDqDeqWidth = 4, 145 LsDqDeqWidth = 4 146 ), 147 exuParameters: ExuParameters = ExuParameters( 148 JmpCnt = 1, 149 AluCnt = 4, 150 MulCnt = 0, 151 MduCnt = 2, 152 FmacCnt = 4, 153 FmiscCnt = 2, 154 FmiscDivSqrtCnt = 0, 155 LduCnt = 2, 156 StuCnt = 2 157 ), 158 LoadPipelineWidth: Int = 2, 159 StorePipelineWidth: Int = 2, 160 StoreBufferSize: Int = 16, 161 StoreBufferThreshold: Int = 7, 162 EnableFastForward: Boolean = true, 163 EnableLdVioCheckAfterReset: Boolean = true, 164 RefillSize: Int = 512, 165 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 166 itlbParameters: TLBParameters = TLBParameters( 167 name = "itlb", 168 fetchi = true, 169 useDmode = false, 170 sameCycle = true, 171 normalNWays = 32, 172 normalReplacer = Some("plru"), 173 superNWays = 4, 174 superReplacer = Some("plru"), 175 shouldBlock = true 176 ), 177 ldtlbParameters: TLBParameters = TLBParameters( 178 name = "ldtlb", 179 normalNSets = 128, 180 normalNWays = 1, 181 normalAssociative = "sa", 182 normalReplacer = Some("setplru"), 183 superNWays = 8, 184 normalAsVictim = true, 185 outReplace = true 186 ), 187 sttlbParameters: TLBParameters = TLBParameters( 188 name = "sttlb", 189 normalNSets = 128, 190 normalNWays = 1, 191 normalAssociative = "sa", 192 normalReplacer = Some("setplru"), 193 superNWays = 8, 194 normalAsVictim = true, 195 outReplace = true 196 ), 197 refillBothTlb: Boolean = false, 198 btlbParameters: TLBParameters = TLBParameters( 199 name = "btlb", 200 normalNSets = 1, 201 normalNWays = 64, 202 superNWays = 4, 203 ), 204 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 205 NumPMP: Int = 16, // 0 or 16 or 64 206 NumPMA: Int = 16, 207 NumPerfCounters: Int = 16, 208 icacheParameters: ICacheParameters = ICacheParameters( 209 tagECC = Some("parity"), 210 dataECC = Some("parity"), 211 replacer = Some("setplru"), 212 nMissEntries = 2 213 ), 214 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 215 tagECC = Some("secded"), 216 dataECC = Some("secded"), 217 replacer = Some("setplru"), 218 nMissEntries = 16, 219 nProbeEntries = 8, 220 nReleaseEntries = 18 221 )), 222 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 223 name = "l2", 224 level = 2, 225 ways = 8, 226 sets = 1024, // default 512KB L2 227 prefetch = Some(huancun.prefetch.BOPParameters()) 228 )), 229 L2NBanks: Int = 1, 230 usePTWRepeater: Boolean = false, 231 softPTW: Boolean = false // dpi-c debug only 232){ 233 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 234 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 235 236 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 237 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 238 239 val fpExuConfigs = 240 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 241 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 242 243 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 244} 245 246case object DebugOptionsKey extends Field[DebugOptions] 247 248case class DebugOptions 249( 250 FPGAPlatform: Boolean = true, 251 EnableDebug: Boolean = true, 252 EnablePerfDebug: Boolean = true, 253 UseDRAMSim: Boolean = false 254) 255 256trait HasXSParameter { 257 258 implicit val p: Parameters 259 260 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 261 262 val coreParams = p(XSCoreParamsKey) 263 val env = p(DebugOptionsKey) 264 265 val XLEN = coreParams.XLEN 266 val hardId = coreParams.HartId 267 val minFLen = 32 268 val fLen = 64 269 def xLen = XLEN 270 271 val HasMExtension = coreParams.HasMExtension 272 val HasCExtension = coreParams.HasCExtension 273 val HasDiv = coreParams.HasDiv 274 val HasIcache = coreParams.HasICache 275 val HasDcache = coreParams.HasDCache 276 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 277 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 278 val AsidLength = coreParams.AsidLength 279 val AddrBytes = AddrBits / 8 // unused 280 val DataBits = XLEN 281 val DataBytes = DataBits / 8 282 val HasFPU = coreParams.HasFPU 283 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 284 val FetchWidth = coreParams.FetchWidth 285 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 286 val EnableBPU = coreParams.EnableBPU 287 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 288 val EnableRAS = coreParams.EnableRAS 289 val EnableLB = coreParams.EnableLB 290 val EnableLoop = coreParams.EnableLoop 291 val EnableSC = coreParams.EnableSC 292 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 293 val HistoryLength = coreParams.HistoryLength 294 val PathHistoryLength = coreParams.PathHistoryLength 295 val BtbSize = coreParams.BtbSize 296 // val BtbWays = 4 297 val BtbBanks = PredictWidth 298 // val BtbSets = BtbSize / BtbWays 299 val JbtacSize = coreParams.JbtacSize 300 val JbtacBanks = coreParams.JbtacBanks 301 val RasSize = coreParams.RasSize 302 303 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 304 coreParams.branchPredictor(resp_in, p) 305 } 306 val numBr = coreParams.numBr 307 val TageTableInfos = coreParams.TageTableInfos 308 309 310 val BankTageTableInfos = (0 until numBr).map(i => 311 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 312 ) 313 val SCNRows = coreParams.SCNRows 314 val SCCtrBits = coreParams.SCCtrBits 315 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 316 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 317 318 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 319 case (ntable, histlens) => 320 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 321 } 322 val ITTageTableInfos = coreParams.ITTageTableInfos 323 type FoldedHistoryInfo = Tuple2[Int, Int] 324 val foldedGHistInfos = 325 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 326 if (h > 0) 327 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 328 else 329 Set[FoldedHistoryInfo]() 330 }.reduce(_++_)).toSet ++ 331 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 332 if (h > 0) 333 Set((h, min(log2Ceil(nRows), h))) 334 else 335 Set[FoldedHistoryInfo]() 336 }.reduce(_++_)).toSet ++ 337 ITTageTableInfos.map{ case (nRows, h, t) => 338 if (h > 0) 339 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 340 else 341 Set[FoldedHistoryInfo]() 342 }.reduce(_++_)).toList 343 344 val CacheLineSize = coreParams.CacheLineSize 345 val CacheLineHalfWord = CacheLineSize / 16 346 val ExtHistoryLength = HistoryLength + 64 347 val UBtbWays = coreParams.UBtbWays 348 val BtbWays = coreParams.BtbWays 349 val IBufSize = coreParams.IBufSize 350 val DecodeWidth = coreParams.DecodeWidth 351 val RenameWidth = coreParams.RenameWidth 352 val CommitWidth = coreParams.CommitWidth 353 val FtqSize = coreParams.FtqSize 354 val IssQueSize = coreParams.IssQueSize 355 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 356 val NRPhyRegs = coreParams.NRPhyRegs 357 val PhyRegIdxWidth = log2Up(NRPhyRegs) 358 val RobSize = coreParams.RobSize 359 val IntRefCounterWidth = log2Ceil(RobSize) 360 val StdFreeListSize = NRPhyRegs - 32 361 val MEFreeListSize = NRPhyRegs 362 val LoadQueueSize = coreParams.LoadQueueSize 363 val StoreQueueSize = coreParams.StoreQueueSize 364 val dpParams = coreParams.dpParams 365 val exuParameters = coreParams.exuParameters 366 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 367 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 368 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 369 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 370 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 371 val LoadPipelineWidth = coreParams.LoadPipelineWidth 372 val StorePipelineWidth = coreParams.StorePipelineWidth 373 val StoreBufferSize = coreParams.StoreBufferSize 374 val StoreBufferThreshold = coreParams.StoreBufferThreshold 375 val EnableFastForward = coreParams.EnableFastForward 376 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 377 val RefillSize = coreParams.RefillSize 378 val asidLen = coreParams.MMUAsidLen 379 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 380 val refillBothTlb = coreParams.refillBothTlb 381 val itlbParams = coreParams.itlbParameters 382 val ldtlbParams = coreParams.ldtlbParameters 383 val sttlbParams = coreParams.sttlbParameters 384 val btlbParams = coreParams.btlbParameters 385 val l2tlbParams = coreParams.l2tlbParameters 386 val NumPMP = coreParams.NumPMP 387 val NumPMA = coreParams.NumPMA 388 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 389 val NumPerfCounters = coreParams.NumPerfCounters 390 391 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 392 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 393 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 394 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 395 396 val instBytes = if (HasCExtension) 2 else 4 397 val instOffsetBits = log2Ceil(instBytes) 398 399 val icacheParameters = coreParams.icacheParameters 400 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 401 402 val LRSCCycles = 100 403 404 // cache hierarchy configurations 405 val l1BusDataWidth = 256 406 407 // load violation predict 408 val ResetTimeMax2Pow = 20 //1078576 409 val ResetTimeMin2Pow = 10 //1024 410 // wait table parameters 411 val WaitTableSize = 1024 412 val MemPredPCWidth = log2Up(WaitTableSize) 413 val LWTUse2BitCounter = true 414 // store set parameters 415 val SSITSize = WaitTableSize 416 val LFSTSize = 32 417 val SSIDWidth = log2Up(LFSTSize) 418 val LFSTWidth = 4 419 val StoreSetEnable = true // LWT will be disabled if SS is enabled 420 421 val loadExuConfigs = coreParams.loadExuConfigs 422 val storeExuConfigs = coreParams.storeExuConfigs 423 424 val intExuConfigs = coreParams.intExuConfigs 425 426 val fpExuConfigs = coreParams.fpExuConfigs 427 428 val exuConfigs = coreParams.exuConfigs 429 430 val PCntIncrStep: Int = 6 431 val numPCntHc: Int = 25 432 val numPCntPtw: Int = 19 433 434 val numCSRPCntFrontend = 8 435 val numCSRPCntCtrl = 8 436 val numCSRPCntLsu = 8 437 val numCSRPCntHc = 5 438 val print_perfcounter = false 439} 440