1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 20, 172 LoadNCBufferSize: Int = 20, 173 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 174 StoreQueueSize: Int = 64, 175 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 176 StoreQueueForwardWithMask: Boolean = true, 177 VlsQueueSize: Int = 8, 178 RobSize: Int = 160, 179 RabSize: Int = 256, 180 VTypeBufferSize: Int = 64, // used to reorder vtype 181 IssueQueueSize: Int = 24, 182 IssueQueueCompEntrySize: Int = 16, 183 dpParams: DispatchParameters = DispatchParameters( 184 IntDqSize = 16, 185 FpDqSize = 16, 186 LsDqSize = 18, 187 IntDqDeqWidth = 8, 188 FpDqDeqWidth = 6, 189 VecDqDeqWidth = 6, 190 LsDqDeqWidth = 6, 191 ), 192 intPreg: PregParams = IntPregParams( 193 numEntries = 224, 194 numRead = None, 195 numWrite = None, 196 ), 197 fpPreg: PregParams = FpPregParams( 198 numEntries = 192, 199 numRead = None, 200 numWrite = None, 201 ), 202 vfPreg: VfPregParams = VfPregParams( 203 numEntries = 128, 204 numRead = None, 205 numWrite = None, 206 ), 207 v0Preg: V0PregParams = V0PregParams( 208 numEntries = 22, 209 numRead = None, 210 numWrite = None, 211 ), 212 vlPreg: VlPregParams = VlPregParams( 213 numEntries = 32, 214 numRead = None, 215 numWrite = None, 216 ), 217 IntRegCacheSize: Int = 16, 218 MemRegCacheSize: Int = 12, 219 intSchdVlWbPort: Int = 0, 220 vfSchdVlWbPort: Int = 1, 221 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 222 IfuRedirectNum: Int = 1, 223 LoadPipelineWidth: Int = 3, 224 StorePipelineWidth: Int = 2, 225 VecLoadPipelineWidth: Int = 2, 226 VecStorePipelineWidth: Int = 2, 227 VecMemSrcInWidth: Int = 2, 228 VecMemInstWbWidth: Int = 1, 229 VecMemDispatchWidth: Int = 1, 230 VecMemDispatchMaxNumber: Int = 16, 231 VecMemUnitStrideMaxFlowNum: Int = 2, 232 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 233 StoreBufferSize: Int = 16, 234 StoreBufferThreshold: Int = 7, 235 EnsbufferWidth: Int = 2, 236 LoadDependencyWidth: Int = 2, 237 // ============ VLSU ============ 238 VlMergeBufferSize: Int = 16, 239 VsMergeBufferSize: Int = 16, 240 UopWritebackWidth: Int = 2, 241 VLUopWritebackWidth: Int = 2, 242 VSUopWritebackWidth: Int = 1, 243 VSegmentBufferSize: Int = 8, 244 VFOFBufferSize: Int = 8, 245 VLFOFWritebackWidth: Int = 1, 246 // ============================== 247 UncacheBufferSize: Int = 4, 248 EnableLoadToLoadForward: Boolean = false, 249 EnableFastForward: Boolean = true, 250 EnableLdVioCheckAfterReset: Boolean = true, 251 EnableSoftPrefetchAfterReset: Boolean = true, 252 EnableCacheErrorAfterReset: Boolean = true, 253 EnableAccurateLoadError: Boolean = false, 254 EnableUncacheWriteOutstanding: Boolean = false, 255 EnableHardwareStoreMisalign: Boolean = true, 256 EnableHardwareLoadMisalign: Boolean = true, 257 EnableStorePrefetchAtIssue: Boolean = false, 258 EnableStorePrefetchAtCommit: Boolean = false, 259 EnableAtCommitMissTrigger: Boolean = true, 260 EnableStorePrefetchSMS: Boolean = false, 261 EnableStorePrefetchSPB: Boolean = false, 262 HasCMO: Boolean = true, 263 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 264 MMUVmidLen: Int = 14, 265 ReSelectLen: Int = 7, // load replay queue replay select counter len 266 iwpuParameters: WPUParameters = WPUParameters( 267 enWPU = false, 268 algoName = "mmru", 269 isICache = true, 270 ), 271 dwpuParameters: WPUParameters = WPUParameters( 272 enWPU = false, 273 algoName = "mmru", 274 enCfPred = false, 275 isICache = false, 276 ), 277 itlbParameters: TLBParameters = TLBParameters( 278 name = "itlb", 279 fetchi = true, 280 useDmode = false, 281 NWays = 48, 282 ), 283 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 284 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 285 ldtlbParameters: TLBParameters = TLBParameters( 286 name = "ldtlb", 287 NWays = 48, 288 outReplace = false, 289 partialStaticPMP = true, 290 outsideRecvFlush = true, 291 saveLevel = false, 292 lgMaxSize = 4 293 ), 294 sttlbParameters: TLBParameters = TLBParameters( 295 name = "sttlb", 296 NWays = 48, 297 outReplace = false, 298 partialStaticPMP = true, 299 outsideRecvFlush = true, 300 saveLevel = false, 301 lgMaxSize = 4 302 ), 303 hytlbParameters: TLBParameters = TLBParameters( 304 name = "hytlb", 305 NWays = 48, 306 outReplace = false, 307 partialStaticPMP = true, 308 outsideRecvFlush = true, 309 saveLevel = false, 310 lgMaxSize = 4 311 ), 312 pftlbParameters: TLBParameters = TLBParameters( 313 name = "pftlb", 314 NWays = 48, 315 outReplace = false, 316 partialStaticPMP = true, 317 outsideRecvFlush = true, 318 saveLevel = false, 319 lgMaxSize = 4 320 ), 321 l2ToL1tlbParameters: TLBParameters = TLBParameters( 322 name = "l2tlb", 323 NWays = 48, 324 outReplace = false, 325 partialStaticPMP = true, 326 outsideRecvFlush = true, 327 saveLevel = false 328 ), 329 refillBothTlb: Boolean = false, 330 btlbParameters: TLBParameters = TLBParameters( 331 name = "btlb", 332 NWays = 48, 333 ), 334 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 335 NumPerfCounters: Int = 16, 336 icacheParameters: ICacheParameters = ICacheParameters( 337 tagECC = Some("parity"), 338 dataECC = Some("parity"), 339 replacer = Some("setplru"), 340 ), 341 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 342 tagECC = Some("secded"), 343 dataECC = Some("secded"), 344 replacer = Some("setplru"), 345 nMissEntries = 16, 346 nProbeEntries = 8, 347 nReleaseEntries = 18, 348 nMaxPrefetchEntry = 6, 349 enableTagEcc = true, 350 enableDataEcc = true 351 )), 352 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 353 name = "l2", 354 ways = 8, 355 sets = 1024, // default 512KB L2 356 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 357 coupledL2.prefetch.TPParameters()), 358 )), 359 L2NBanks: Int = 1, 360 usePTWRepeater: Boolean = false, 361 softTLB: Boolean = false, // dpi-c l1tlb debug only 362 softPTW: Boolean = false, // dpi-c l2tlb debug only 363 softPTWDelay: Int = 1 364){ 365 def ISABase = "rv64i" 366 def ISAExtensions = Seq( 367 // single letter extensions, in canonical order 368 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 369 // multi-letter extensions, sorted alphanumerically 370 "sdtrig", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", 371 "smaia", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssstateen", 372 "sstc", "sstvala", "sstvecd", "ssu64xl", "sv39", "sv48", "svade", "svbare", "svinval", 373 "svpbmt", "za64rs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", 374 "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccif", "zicclsm", 375 "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zimop", "zkn", 376 "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", 377 "zvl128b", "zvl32b", "zvl64b" 378 ) 379 380 def vlWidth = log2Up(VLEN) + 1 381 382 /** 383 * the minimum element length of vector elements 384 */ 385 val minVecElen: Int = 8 386 387 /** 388 * the maximum number of elements in vector register 389 */ 390 val maxElemPerVreg: Int = VLEN / minVecElen 391 392 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 393 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 394 395 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 396 val RegCacheIdxWidth = log2Up(RegCacheSize) 397 398 val intSchdParams = { 399 implicit val schdType: SchedulerType = IntScheduler() 400 SchdBlockParams(Seq( 401 IssueBlockParams(Seq( 402 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 403 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 407 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 408 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 409 IssueBlockParams(Seq( 410 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 411 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 412 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 413 IssueBlockParams(Seq( 414 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 415 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 416 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 417 ), 418 numPregs = intPreg.numEntries, 419 numDeqOutside = 0, 420 schdType = schdType, 421 rfDataWidth = intPreg.dataCfg.dataWidth, 422 numUopIn = dpParams.IntDqDeqWidth, 423 ) 424 } 425 426 val fpSchdParams = { 427 implicit val schdType: SchedulerType = FpScheduler() 428 SchdBlockParams(Seq( 429 IssueBlockParams(Seq( 430 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 431 ), numEntries = 18, numEnq = 2, numComp = 16), 432 IssueBlockParams(Seq( 433 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 434 ), numEntries = 18, numEnq = 2, numComp = 16), 435 IssueBlockParams(Seq( 436 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 437 ), numEntries = 18, numEnq = 2, numComp = 16), 438 IssueBlockParams(Seq( 439 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 440 ), numEntries = 18, numEnq = 2, numComp = 16), 441 IssueBlockParams(Seq( 442 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 443 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 444 ), numEntries = 18, numEnq = 2, numComp = 16), 445 ), 446 numPregs = fpPreg.numEntries, 447 numDeqOutside = 0, 448 schdType = schdType, 449 rfDataWidth = fpPreg.dataCfg.dataWidth, 450 numUopIn = dpParams.FpDqDeqWidth, 451 ) 452 } 453 454 val vfSchdParams = { 455 implicit val schdType: SchedulerType = VfScheduler() 456 SchdBlockParams(Seq( 457 IssueBlockParams(Seq( 458 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 459 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 463 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 464 ), numEntries = 16, numEnq = 2, numComp = 14), 465 IssueBlockParams(Seq( 466 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 467 ), numEntries = 10, numEnq = 2, numComp = 8), 468 ), 469 numPregs = vfPreg.numEntries, 470 numDeqOutside = 0, 471 schdType = schdType, 472 rfDataWidth = vfPreg.dataCfg.dataWidth, 473 numUopIn = dpParams.VecDqDeqWidth, 474 ) 475 } 476 477 val memSchdParams = { 478 implicit val schdType: SchedulerType = MemScheduler() 479 val rfDataWidth = 64 480 481 SchdBlockParams(Seq( 482 IssueBlockParams(Seq( 483 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 484 ), numEntries = 16, numEnq = 1, numComp = 15), 485 IssueBlockParams(Seq( 486 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 487 ), numEntries = 16, numEnq = 1, numComp = 15), 488 IssueBlockParams(Seq( 489 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 490 ), numEntries = 16, numEnq = 1, numComp = 15), 491 IssueBlockParams(Seq( 492 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 493 ), numEntries = 16, numEnq = 1, numComp = 15), 494 IssueBlockParams(Seq( 495 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 496 ), numEntries = 16, numEnq = 1, numComp = 15), 497 IssueBlockParams(Seq( 498 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 499 ), numEntries = 16, numEnq = 1, numComp = 15), 500 IssueBlockParams(Seq( 501 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 502 ), numEntries = 16, numEnq = 1, numComp = 15), 503 IssueBlockParams(Seq( 504 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 505 ), numEntries = 16, numEnq = 1, numComp = 15), 506 IssueBlockParams(Seq( 507 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 508 ), numEntries = 16, numEnq = 1, numComp = 15), 509 ), 510 numPregs = intPreg.numEntries max vfPreg.numEntries, 511 numDeqOutside = 0, 512 schdType = schdType, 513 rfDataWidth = rfDataWidth, 514 numUopIn = dpParams.LsDqDeqWidth, 515 ) 516 } 517 518 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 519 520 def iqWakeUpParams = { 521 Seq( 522 WakeUpConfig( 523 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 524 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 525 ), 526 // TODO: add load -> fp slow wakeup 527 WakeUpConfig( 528 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 529 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 530 ), 531 WakeUpConfig( 532 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 533 Seq("STD0", "STD1") 534 ), 535// WakeUpConfig( 536// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 537// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 538// ), 539 ).flatten 540 } 541 542 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 543 544 val backendParams: BackendParams = backend.BackendParams( 545 Map( 546 IntScheduler() -> intSchdParams, 547 FpScheduler() -> fpSchdParams, 548 VfScheduler() -> vfSchdParams, 549 MemScheduler() -> memSchdParams, 550 ), 551 Seq( 552 intPreg, 553 fpPreg, 554 vfPreg, 555 v0Preg, 556 vlPreg, 557 fakeIntPreg 558 ), 559 iqWakeUpParams, 560 ) 561 562 // Parameters for trace extension. 563 // Trace parameters is useful for XSTOP. 564 val TraceGroupNum = 3 // Width to Encoder 565} 566 567case object DebugOptionsKey extends Field[DebugOptions] 568 569case class DebugOptions 570( 571 FPGAPlatform: Boolean = false, 572 ResetGen: Boolean = false, 573 EnableDifftest: Boolean = false, 574 AlwaysBasicDiff: Boolean = true, 575 EnableDebug: Boolean = false, 576 EnablePerfDebug: Boolean = true, 577 UseDRAMSim: Boolean = false, 578 EnableConstantin: Boolean = false, 579 EnableChiselDB: Boolean = false, 580 AlwaysBasicDB: Boolean = true, 581 EnableRollingDB: Boolean = false 582) 583 584trait HasXSParameter { 585 586 implicit val p: Parameters 587 588 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 589 def PmemRanges = p(SoCParamsKey).PmemRanges 590 def PmemLowBounds = PmemRanges.unzip._1 591 def PmemHighBounds = PmemRanges.unzip._2 592 final val PageOffsetWidth = 12 593 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 594 595 def coreParams = p(XSCoreParamsKey) 596 def env = p(DebugOptionsKey) 597 598 def ISABase = coreParams.ISABase 599 def ISAExtensions = coreParams.ISAExtensions 600 def XLEN = coreParams.XLEN 601 def VLEN = coreParams.VLEN 602 def ELEN = coreParams.ELEN 603 def HSXLEN = coreParams.HSXLEN 604 val minFLen = 32 605 val fLen = 64 606 def hartIdLen = p(MaxHartIdBits) 607 val xLen = XLEN 608 609 def HasMExtension = coreParams.HasMExtension 610 def HasCExtension = coreParams.HasCExtension 611 def HasHExtension = coreParams.HasHExtension 612 def EnableSv48 = coreParams.EnableSv48 613 def HasDiv = coreParams.HasDiv 614 def HasIcache = coreParams.HasICache 615 def HasDcache = coreParams.HasDCache 616 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 617 def PAddrBitsMax = coreParams.PAddrBitsMax 618 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 619 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 620 def GPAddrBits = { 621 if (EnableSv48) 622 coreParams.GPAddrBitsSv48x4 623 else 624 coreParams.GPAddrBitsSv39x4 625 } 626 def VAddrBits = { 627 if (HasHExtension) { 628 if (EnableSv48) 629 coreParams.GPAddrBitsSv48x4 630 else 631 coreParams.GPAddrBitsSv39x4 632 } else { 633 if (EnableSv48) 634 coreParams.VAddrBitsSv48 635 else 636 coreParams.VAddrBitsSv39 637 } 638 } // VAddrBits is Virtual Memory addr bits 639 640 def VAddrMaxBits = { 641 if(EnableSv48) { 642 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 643 } else { 644 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 645 } 646 } 647 648 def AsidLength = coreParams.AsidLength 649 def VmidLength = coreParams.VmidLength 650 def ReSelectLen = coreParams.ReSelectLen 651 def AddrBytes = AddrBits / 8 // unused 652 def DataBits = XLEN 653 def DataBytes = DataBits / 8 654 def VDataBytes = VLEN / 8 655 def HasFPU = coreParams.HasFPU 656 def HasVPU = coreParams.HasVPU 657 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 658 def FetchWidth = coreParams.FetchWidth 659 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 660 def EnableBPU = coreParams.EnableBPU 661 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 662 def EnableRAS = coreParams.EnableRAS 663 def EnableLB = coreParams.EnableLB 664 def EnableLoop = coreParams.EnableLoop 665 def EnableSC = coreParams.EnableSC 666 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 667 def HistoryLength = coreParams.HistoryLength 668 def EnableGHistDiff = coreParams.EnableGHistDiff 669 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 670 def EnableClockGate = coreParams.EnableClockGate 671 def UbtbGHRLength = coreParams.UbtbGHRLength 672 def UbtbSize = coreParams.UbtbSize 673 def EnableFauFTB = coreParams.EnableFauFTB 674 def FtbSize = coreParams.FtbSize 675 def FtbWays = coreParams.FtbWays 676 def FtbTagLength = coreParams.FtbTagLength 677 def RasSize = coreParams.RasSize 678 def RasSpecSize = coreParams.RasSpecSize 679 def RasCtrSize = coreParams.RasCtrSize 680 681 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 682 coreParams.branchPredictor(resp_in, p) 683 } 684 def numBr = coreParams.numBr 685 def TageTableInfos = coreParams.TageTableInfos 686 def TageBanks = coreParams.numBr 687 def SCNRows = coreParams.SCNRows 688 def SCCtrBits = coreParams.SCCtrBits 689 def SCHistLens = coreParams.SCHistLens 690 def SCNTables = coreParams.SCNTables 691 692 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 693 case ((n, cb), h) => (n, cb, h) 694 } 695 def ITTageTableInfos = coreParams.ITTageTableInfos 696 type FoldedHistoryInfo = Tuple2[Int, Int] 697 def foldedGHistInfos = 698 (TageTableInfos.map{ case (nRows, h, t) => 699 if (h > 0) 700 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 701 else 702 Set[FoldedHistoryInfo]() 703 }.reduce(_++_).toSet ++ 704 SCTableInfos.map{ case (nRows, _, h) => 705 if (h > 0) 706 Set((h, min(log2Ceil(nRows/TageBanks), h))) 707 else 708 Set[FoldedHistoryInfo]() 709 }.reduce(_++_).toSet ++ 710 ITTageTableInfos.map{ case (nRows, h, t) => 711 if (h > 0) 712 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 713 else 714 Set[FoldedHistoryInfo]() 715 }.reduce(_++_) ++ 716 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 717 ).toList 718 719 720 721 def CacheLineSize = coreParams.CacheLineSize 722 def CacheLineHalfWord = CacheLineSize / 16 723 def ExtHistoryLength = HistoryLength + 64 724 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 725 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 726 def IBufSize = coreParams.IBufSize 727 def IBufNBank = coreParams.IBufNBank 728 def backendParams: BackendParams = coreParams.backendParams 729 def DecodeWidth = coreParams.DecodeWidth 730 def RenameWidth = coreParams.RenameWidth 731 def CommitWidth = coreParams.CommitWidth 732 def RobCommitWidth = coreParams.RobCommitWidth 733 def RabCommitWidth = coreParams.RabCommitWidth 734 def MaxUopSize = coreParams.MaxUopSize 735 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 736 def RenameSnapshotNum = coreParams.RenameSnapshotNum 737 def FtqSize = coreParams.FtqSize 738 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 739 def IntLogicRegs = coreParams.IntLogicRegs 740 def FpLogicRegs = coreParams.FpLogicRegs 741 def VecLogicRegs = coreParams.VecLogicRegs 742 def V0LogicRegs = coreParams.V0LogicRegs 743 def VlLogicRegs = coreParams.VlLogicRegs 744 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 745 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 746 def V0_IDX = coreParams.V0_IDX 747 def Vl_IDX = coreParams.Vl_IDX 748 def IntPhyRegs = coreParams.intPreg.numEntries 749 def FpPhyRegs = coreParams.fpPreg.numEntries 750 def VfPhyRegs = coreParams.vfPreg.numEntries 751 def V0PhyRegs = coreParams.v0Preg.numEntries 752 def VlPhyRegs = coreParams.vlPreg.numEntries 753 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 754 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 755 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 756 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 757 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 758 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 759 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 760 def RobSize = coreParams.RobSize 761 def RabSize = coreParams.RabSize 762 def VTypeBufferSize = coreParams.VTypeBufferSize 763 def IntRegCacheSize = coreParams.IntRegCacheSize 764 def MemRegCacheSize = coreParams.MemRegCacheSize 765 def RegCacheSize = coreParams.RegCacheSize 766 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 767 /** 768 * the minimum element length of vector elements 769 */ 770 def minVecElen: Int = coreParams.minVecElen 771 772 /** 773 * the maximum number of elements in vector register 774 */ 775 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 776 777 def IntRefCounterWidth = log2Ceil(RobSize) 778 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 779 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 780 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 781 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 782 def LoadQueueRARSize = coreParams.LoadQueueRARSize 783 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 784 def RollbackGroupSize = coreParams.RollbackGroupSize 785 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 786 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 787 def LoadNCBufferSize = coreParams.LoadNCBufferSize 788 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 789 def StoreQueueSize = coreParams.StoreQueueSize 790 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 791 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 792 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 793 def VlsQueueSize = coreParams.VlsQueueSize 794 def dpParams = coreParams.dpParams 795 796 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 797 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 798 799 def NumRedirect = backendParams.numRedirect 800 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 801 def FtqRedirectAheadNum = NumRedirect 802 def IfuRedirectNum = coreParams.IfuRedirectNum 803 def LoadPipelineWidth = coreParams.LoadPipelineWidth 804 def StorePipelineWidth = coreParams.StorePipelineWidth 805 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 806 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 807 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 808 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 809 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 810 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 811 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 812 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 813 def StoreBufferSize = coreParams.StoreBufferSize 814 def StoreBufferThreshold = coreParams.StoreBufferThreshold 815 def EnsbufferWidth = coreParams.EnsbufferWidth 816 def LoadDependencyWidth = coreParams.LoadDependencyWidth 817 def VlMergeBufferSize = coreParams.VlMergeBufferSize 818 def VsMergeBufferSize = coreParams.VsMergeBufferSize 819 def UopWritebackWidth = coreParams.UopWritebackWidth 820 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 821 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 822 def VSegmentBufferSize = coreParams.VSegmentBufferSize 823 def VFOFBufferSize = coreParams.VFOFBufferSize 824 def UncacheBufferSize = coreParams.UncacheBufferSize 825 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 826 def EnableFastForward = coreParams.EnableFastForward 827 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 828 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 829 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 830 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 831 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 832 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 833 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 834 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 835 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 836 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 837 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 838 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 839 def HasCMO = coreParams.HasCMO && p(EnableCHI) 840 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 841 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 842 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 843 def asidLen = coreParams.MMUAsidLen 844 def vmidLen = coreParams.MMUVmidLen 845 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 846 def refillBothTlb = coreParams.refillBothTlb 847 def iwpuParam = coreParams.iwpuParameters 848 def dwpuParam = coreParams.dwpuParameters 849 def itlbParams = coreParams.itlbParameters 850 def ldtlbParams = coreParams.ldtlbParameters 851 def sttlbParams = coreParams.sttlbParameters 852 def hytlbParams = coreParams.hytlbParameters 853 def pftlbParams = coreParams.pftlbParameters 854 def l2ToL1Params = coreParams.l2ToL1tlbParameters 855 def btlbParams = coreParams.btlbParameters 856 def l2tlbParams = coreParams.l2tlbParameters 857 def NumPerfCounters = coreParams.NumPerfCounters 858 859 def instBytes = if (HasCExtension) 2 else 4 860 def instOffsetBits = log2Ceil(instBytes) 861 862 def icacheParameters = coreParams.icacheParameters 863 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 864 865 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 866 // for constrained LR/SC loop 867 def LRSCCycles = 64 868 // for lr storm 869 def LRSCBackOff = 8 870 871 // cache hierarchy configurations 872 def l1BusDataWidth = 256 873 874 // load violation predict 875 def ResetTimeMax2Pow = 20 //1078576 876 def ResetTimeMin2Pow = 10 //1024 877 // wait table parameters 878 def WaitTableSize = 1024 879 def MemPredPCWidth = log2Up(WaitTableSize) 880 def LWTUse2BitCounter = true 881 // store set parameters 882 def SSITSize = WaitTableSize 883 def LFSTSize = 32 884 def SSIDWidth = log2Up(LFSTSize) 885 def LFSTWidth = 4 886 def StoreSetEnable = true // LWT will be disabled if SS is enabled 887 def LFSTEnable = true 888 889 def PCntIncrStep: Int = 6 890 def numPCntHc: Int = 12 891 def numPCntPtw: Int = 19 892 893 def numCSRPCntFrontend = 8 894 def numCSRPCntCtrl = 8 895 def numCSRPCntLsu = 8 896 def numCSRPCntHc = 5 897 def printEventCoding = true 898 def printCriticalError = false 899 def maxCommitStuck = pow(2, 21).toInt 900 901 // Vector load exception 902 def maxMergeNumPerCycle = 4 903 904 // Parameters for Sdtrig extension 905 protected def TriggerNum = 4 906 protected def TriggerChainMaxLength = 2 907 908 // Parameters for Trace extension 909 def TraceGroupNum = coreParams.TraceGroupNum 910} 911