1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 20, 172 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 173 StoreQueueSize: Int = 64, 174 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 175 StoreQueueForwardWithMask: Boolean = true, 176 VlsQueueSize: Int = 8, 177 RobSize: Int = 160, 178 RabSize: Int = 256, 179 VTypeBufferSize: Int = 64, // used to reorder vtype 180 IssueQueueSize: Int = 24, 181 IssueQueueCompEntrySize: Int = 16, 182 dpParams: DispatchParameters = DispatchParameters( 183 IntDqSize = 16, 184 FpDqSize = 16, 185 LsDqSize = 18, 186 IntDqDeqWidth = 8, 187 FpDqDeqWidth = 6, 188 VecDqDeqWidth = 6, 189 LsDqDeqWidth = 6, 190 ), 191 intPreg: PregParams = IntPregParams( 192 numEntries = 224, 193 numRead = None, 194 numWrite = None, 195 ), 196 fpPreg: PregParams = FpPregParams( 197 numEntries = 192, 198 numRead = None, 199 numWrite = None, 200 ), 201 vfPreg: VfPregParams = VfPregParams( 202 numEntries = 128, 203 numRead = None, 204 numWrite = None, 205 ), 206 v0Preg: V0PregParams = V0PregParams( 207 numEntries = 22, 208 numRead = None, 209 numWrite = None, 210 ), 211 vlPreg: VlPregParams = VlPregParams( 212 numEntries = 32, 213 numRead = None, 214 numWrite = None, 215 ), 216 IntRegCacheSize: Int = 16, 217 MemRegCacheSize: Int = 12, 218 intSchdVlWbPort: Int = 0, 219 vfSchdVlWbPort: Int = 1, 220 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 221 IfuRedirectNum: Int = 1, 222 LoadPipelineWidth: Int = 3, 223 StorePipelineWidth: Int = 2, 224 VecLoadPipelineWidth: Int = 2, 225 VecStorePipelineWidth: Int = 2, 226 VecMemSrcInWidth: Int = 2, 227 VecMemInstWbWidth: Int = 1, 228 VecMemDispatchWidth: Int = 1, 229 VecMemDispatchMaxNumber: Int = 16, 230 VecMemUnitStrideMaxFlowNum: Int = 2, 231 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 232 StoreBufferSize: Int = 16, 233 StoreBufferThreshold: Int = 7, 234 EnsbufferWidth: Int = 2, 235 LoadDependencyWidth: Int = 2, 236 // ============ VLSU ============ 237 VlMergeBufferSize: Int = 16, 238 VsMergeBufferSize: Int = 16, 239 UopWritebackWidth: Int = 2, 240 VLUopWritebackWidth: Int = 2, 241 VSUopWritebackWidth: Int = 1, 242 VSegmentBufferSize: Int = 8, 243 VFOFBufferSize: Int = 8, 244 VLFOFWritebackWidth: Int = 1, 245 // ============================== 246 UncacheBufferSize: Int = 4, 247 EnableLoadToLoadForward: Boolean = false, 248 EnableFastForward: Boolean = true, 249 EnableLdVioCheckAfterReset: Boolean = true, 250 EnableSoftPrefetchAfterReset: Boolean = true, 251 EnableCacheErrorAfterReset: Boolean = true, 252 EnableAccurateLoadError: Boolean = false, 253 EnableUncacheWriteOutstanding: Boolean = false, 254 EnableHardwareStoreMisalign: Boolean = true, 255 EnableHardwareLoadMisalign: Boolean = true, 256 EnableStorePrefetchAtIssue: Boolean = false, 257 EnableStorePrefetchAtCommit: Boolean = false, 258 EnableAtCommitMissTrigger: Boolean = true, 259 EnableStorePrefetchSMS: Boolean = false, 260 EnableStorePrefetchSPB: Boolean = false, 261 HasCMO: Boolean = true, 262 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 263 MMUVmidLen: Int = 14, 264 ReSelectLen: Int = 7, // load replay queue replay select counter len 265 iwpuParameters: WPUParameters = WPUParameters( 266 enWPU = false, 267 algoName = "mmru", 268 isICache = true, 269 ), 270 dwpuParameters: WPUParameters = WPUParameters( 271 enWPU = false, 272 algoName = "mmru", 273 enCfPred = false, 274 isICache = false, 275 ), 276 itlbParameters: TLBParameters = TLBParameters( 277 name = "itlb", 278 fetchi = true, 279 useDmode = false, 280 NWays = 48, 281 ), 282 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 283 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 284 ldtlbParameters: TLBParameters = TLBParameters( 285 name = "ldtlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 sttlbParameters: TLBParameters = TLBParameters( 294 name = "sttlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 hytlbParameters: TLBParameters = TLBParameters( 303 name = "hytlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 pftlbParameters: TLBParameters = TLBParameters( 312 name = "pftlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false, 318 lgMaxSize = 4 319 ), 320 l2ToL1tlbParameters: TLBParameters = TLBParameters( 321 name = "l2tlb", 322 NWays = 48, 323 outReplace = false, 324 partialStaticPMP = true, 325 outsideRecvFlush = true, 326 saveLevel = false 327 ), 328 refillBothTlb: Boolean = false, 329 btlbParameters: TLBParameters = TLBParameters( 330 name = "btlb", 331 NWays = 48, 332 ), 333 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 334 NumPerfCounters: Int = 16, 335 icacheParameters: ICacheParameters = ICacheParameters( 336 tagECC = Some("parity"), 337 dataECC = Some("parity"), 338 replacer = Some("setplru"), 339 ), 340 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 341 tagECC = Some("secded"), 342 dataECC = Some("secded"), 343 replacer = Some("setplru"), 344 nMissEntries = 16, 345 nProbeEntries = 8, 346 nReleaseEntries = 18, 347 nMaxPrefetchEntry = 6, 348 enableTagEcc = true, 349 enableDataEcc = true, 350 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 351 )), 352 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 353 name = "l2", 354 ways = 8, 355 sets = 1024, // default 512KB L2 356 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 357 coupledL2.prefetch.TPParameters()), 358 )), 359 L2NBanks: Int = 1, 360 usePTWRepeater: Boolean = false, 361 softTLB: Boolean = false, // dpi-c l1tlb debug only 362 softPTW: Boolean = false, // dpi-c l2tlb debug only 363 softPTWDelay: Int = 1 364){ 365 def ISABase = "rv64i" 366 def ISAExtensions = Seq( 367 // single letter extensions, in canonical order 368 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 369 // multi-letter extensions, sorted alphanumerically 370 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 371 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 372 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 373 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 374 "sv48", "svade", "svbare", "svinval", "svpbmt", "za64rs", "zacas", "zba", "zbb", "zbc", "zbkb", 375 "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", 376 "zicboz", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", 377 "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", 378 "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 379 ) 380 381 def vlWidth = log2Up(VLEN) + 1 382 383 /** 384 * the minimum element length of vector elements 385 */ 386 val minVecElen: Int = 8 387 388 /** 389 * the maximum number of elements in vector register 390 */ 391 val maxElemPerVreg: Int = VLEN / minVecElen 392 393 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 394 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 395 396 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 397 val RegCacheIdxWidth = log2Up(RegCacheSize) 398 399 val intSchdParams = { 400 implicit val schdType: SchedulerType = IntScheduler() 401 SchdBlockParams(Seq( 402 IssueBlockParams(Seq( 403 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 404 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 405 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 406 IssueBlockParams(Seq( 407 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 408 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 IssueBlockParams(Seq( 411 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 412 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 413 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 414 IssueBlockParams(Seq( 415 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 416 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 417 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 418 ), 419 numPregs = intPreg.numEntries, 420 numDeqOutside = 0, 421 schdType = schdType, 422 rfDataWidth = intPreg.dataCfg.dataWidth, 423 numUopIn = dpParams.IntDqDeqWidth, 424 ) 425 } 426 427 val fpSchdParams = { 428 implicit val schdType: SchedulerType = FpScheduler() 429 SchdBlockParams(Seq( 430 IssueBlockParams(Seq( 431 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 432 ), numEntries = 18, numEnq = 2, numComp = 16), 433 IssueBlockParams(Seq( 434 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 435 ), numEntries = 18, numEnq = 2, numComp = 16), 436 IssueBlockParams(Seq( 437 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 438 ), numEntries = 18, numEnq = 2, numComp = 16), 439 IssueBlockParams(Seq( 440 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 441 ), numEntries = 18, numEnq = 2, numComp = 16), 442 IssueBlockParams(Seq( 443 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 444 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 445 ), numEntries = 18, numEnq = 2, numComp = 16), 446 ), 447 numPregs = fpPreg.numEntries, 448 numDeqOutside = 0, 449 schdType = schdType, 450 rfDataWidth = fpPreg.dataCfg.dataWidth, 451 numUopIn = dpParams.FpDqDeqWidth, 452 ) 453 } 454 455 val vfSchdParams = { 456 implicit val schdType: SchedulerType = VfScheduler() 457 SchdBlockParams(Seq( 458 IssueBlockParams(Seq( 459 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 460 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 461 ), numEntries = 16, numEnq = 2, numComp = 14), 462 IssueBlockParams(Seq( 463 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 464 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 465 ), numEntries = 16, numEnq = 2, numComp = 14), 466 IssueBlockParams(Seq( 467 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 468 ), numEntries = 10, numEnq = 2, numComp = 8), 469 ), 470 numPregs = vfPreg.numEntries, 471 numDeqOutside = 0, 472 schdType = schdType, 473 rfDataWidth = vfPreg.dataCfg.dataWidth, 474 numUopIn = dpParams.VecDqDeqWidth, 475 ) 476 } 477 478 val memSchdParams = { 479 implicit val schdType: SchedulerType = MemScheduler() 480 val rfDataWidth = 64 481 482 SchdBlockParams(Seq( 483 IssueBlockParams(Seq( 484 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 485 ), numEntries = 16, numEnq = 1, numComp = 15), 486 IssueBlockParams(Seq( 487 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 488 ), numEntries = 16, numEnq = 1, numComp = 15), 489 IssueBlockParams(Seq( 490 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 491 ), numEntries = 16, numEnq = 1, numComp = 15), 492 IssueBlockParams(Seq( 493 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 494 ), numEntries = 16, numEnq = 1, numComp = 15), 495 IssueBlockParams(Seq( 496 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 497 ), numEntries = 16, numEnq = 1, numComp = 15), 498 IssueBlockParams(Seq( 499 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 500 ), numEntries = 16, numEnq = 1, numComp = 15), 501 IssueBlockParams(Seq( 502 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 503 ), numEntries = 16, numEnq = 1, numComp = 15), 504 IssueBlockParams(Seq( 505 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 506 ), numEntries = 16, numEnq = 1, numComp = 15), 507 IssueBlockParams(Seq( 508 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 509 ), numEntries = 16, numEnq = 1, numComp = 15), 510 ), 511 numPregs = intPreg.numEntries max vfPreg.numEntries, 512 numDeqOutside = 0, 513 schdType = schdType, 514 rfDataWidth = rfDataWidth, 515 numUopIn = dpParams.LsDqDeqWidth, 516 ) 517 } 518 519 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 520 521 def iqWakeUpParams = { 522 Seq( 523 WakeUpConfig( 524 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 525 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 526 ), 527 // TODO: add load -> fp slow wakeup 528 WakeUpConfig( 529 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 530 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 531 ), 532 WakeUpConfig( 533 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 534 Seq("STD0", "STD1") 535 ), 536// WakeUpConfig( 537// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 538// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 539// ), 540 ).flatten 541 } 542 543 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 544 545 val backendParams: BackendParams = backend.BackendParams( 546 Map( 547 IntScheduler() -> intSchdParams, 548 FpScheduler() -> fpSchdParams, 549 VfScheduler() -> vfSchdParams, 550 MemScheduler() -> memSchdParams, 551 ), 552 Seq( 553 intPreg, 554 fpPreg, 555 vfPreg, 556 v0Preg, 557 vlPreg, 558 fakeIntPreg 559 ), 560 iqWakeUpParams, 561 ) 562 563 // Parameters for trace extension. 564 // Trace parameters is useful for XSTOP. 565 val traceParams: TraceParams = new TraceParams( 566 TraceGroupNum = 3, 567 IaddrWidth = GPAddrBitsSv48x4, 568 PrivWidth = 3, 569 ItypeWidth = 4, 570 IlastsizeWidth = 1, 571 ) 572} 573 574case object DebugOptionsKey extends Field[DebugOptions] 575 576case class DebugOptions 577( 578 FPGAPlatform: Boolean = false, 579 ResetGen: Boolean = false, 580 EnableDifftest: Boolean = false, 581 AlwaysBasicDiff: Boolean = true, 582 EnableDebug: Boolean = false, 583 EnablePerfDebug: Boolean = true, 584 UseDRAMSim: Boolean = false, 585 EnableConstantin: Boolean = false, 586 EnableChiselDB: Boolean = false, 587 AlwaysBasicDB: Boolean = true, 588 EnableRollingDB: Boolean = false 589) 590 591trait HasXSParameter { 592 593 implicit val p: Parameters 594 595 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 596 def PmemRanges = p(SoCParamsKey).PmemRanges 597 def PmemLowBounds = PmemRanges.unzip._1 598 def PmemHighBounds = PmemRanges.unzip._2 599 final val PageOffsetWidth = 12 600 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 601 602 def coreParams = p(XSCoreParamsKey) 603 def env = p(DebugOptionsKey) 604 605 def ISABase = coreParams.ISABase 606 def ISAExtensions = coreParams.ISAExtensions 607 def XLEN = coreParams.XLEN 608 def VLEN = coreParams.VLEN 609 def ELEN = coreParams.ELEN 610 def HSXLEN = coreParams.HSXLEN 611 val minFLen = 32 612 val fLen = 64 613 def hartIdLen = p(MaxHartIdBits) 614 val xLen = XLEN 615 616 def HasMExtension = coreParams.HasMExtension 617 def HasCExtension = coreParams.HasCExtension 618 def HasHExtension = coreParams.HasHExtension 619 def EnableSv48 = coreParams.EnableSv48 620 def HasDiv = coreParams.HasDiv 621 def HasIcache = coreParams.HasICache 622 def HasDcache = coreParams.HasDCache 623 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 624 def PAddrBitsMax = coreParams.PAddrBitsMax 625 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 626 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 627 def GPAddrBits = { 628 if (EnableSv48) 629 coreParams.GPAddrBitsSv48x4 630 else 631 coreParams.GPAddrBitsSv39x4 632 } 633 def VAddrBits = { 634 if (HasHExtension) { 635 if (EnableSv48) 636 coreParams.GPAddrBitsSv48x4 637 else 638 coreParams.GPAddrBitsSv39x4 639 } else { 640 if (EnableSv48) 641 coreParams.VAddrBitsSv48 642 else 643 coreParams.VAddrBitsSv39 644 } 645 } // VAddrBits is Virtual Memory addr bits 646 647 def VAddrMaxBits = { 648 if(EnableSv48) { 649 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 650 } else { 651 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 652 } 653 } 654 655 def AsidLength = coreParams.AsidLength 656 def VmidLength = coreParams.VmidLength 657 def ReSelectLen = coreParams.ReSelectLen 658 def AddrBytes = AddrBits / 8 // unused 659 def DataBits = XLEN 660 def DataBytes = DataBits / 8 661 def QuadWordBits = DataBits * 2 662 def QuadWordBytes = QuadWordBits / 8 663 def VDataBytes = VLEN / 8 664 def HasFPU = coreParams.HasFPU 665 def HasVPU = coreParams.HasVPU 666 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 667 def FetchWidth = coreParams.FetchWidth 668 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 669 def EnableBPU = coreParams.EnableBPU 670 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 671 def EnableRAS = coreParams.EnableRAS 672 def EnableLB = coreParams.EnableLB 673 def EnableLoop = coreParams.EnableLoop 674 def EnableSC = coreParams.EnableSC 675 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 676 def HistoryLength = coreParams.HistoryLength 677 def EnableGHistDiff = coreParams.EnableGHistDiff 678 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 679 def EnableClockGate = coreParams.EnableClockGate 680 def UbtbGHRLength = coreParams.UbtbGHRLength 681 def UbtbSize = coreParams.UbtbSize 682 def EnableFauFTB = coreParams.EnableFauFTB 683 def FtbSize = coreParams.FtbSize 684 def FtbWays = coreParams.FtbWays 685 def FtbTagLength = coreParams.FtbTagLength 686 def RasSize = coreParams.RasSize 687 def RasSpecSize = coreParams.RasSpecSize 688 def RasCtrSize = coreParams.RasCtrSize 689 690 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 691 coreParams.branchPredictor(resp_in, p) 692 } 693 def numBr = coreParams.numBr 694 def TageTableInfos = coreParams.TageTableInfos 695 def TageBanks = coreParams.numBr 696 def SCNRows = coreParams.SCNRows 697 def SCCtrBits = coreParams.SCCtrBits 698 def SCHistLens = coreParams.SCHistLens 699 def SCNTables = coreParams.SCNTables 700 701 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 702 case ((n, cb), h) => (n, cb, h) 703 } 704 def ITTageTableInfos = coreParams.ITTageTableInfos 705 type FoldedHistoryInfo = Tuple2[Int, Int] 706 def foldedGHistInfos = 707 (TageTableInfos.map{ case (nRows, h, t) => 708 if (h > 0) 709 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 710 else 711 Set[FoldedHistoryInfo]() 712 }.reduce(_++_).toSet ++ 713 SCTableInfos.map{ case (nRows, _, h) => 714 if (h > 0) 715 Set((h, min(log2Ceil(nRows/TageBanks), h))) 716 else 717 Set[FoldedHistoryInfo]() 718 }.reduce(_++_).toSet ++ 719 ITTageTableInfos.map{ case (nRows, h, t) => 720 if (h > 0) 721 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 722 else 723 Set[FoldedHistoryInfo]() 724 }.reduce(_++_) ++ 725 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 726 ).toList 727 728 729 730 def CacheLineSize = coreParams.CacheLineSize 731 def CacheLineHalfWord = CacheLineSize / 16 732 def ExtHistoryLength = HistoryLength + 64 733 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 734 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 735 def IBufSize = coreParams.IBufSize 736 def IBufNBank = coreParams.IBufNBank 737 def backendParams: BackendParams = coreParams.backendParams 738 def DecodeWidth = coreParams.DecodeWidth 739 def RenameWidth = coreParams.RenameWidth 740 def CommitWidth = coreParams.CommitWidth 741 def RobCommitWidth = coreParams.RobCommitWidth 742 def RabCommitWidth = coreParams.RabCommitWidth 743 def MaxUopSize = coreParams.MaxUopSize 744 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 745 def RenameSnapshotNum = coreParams.RenameSnapshotNum 746 def FtqSize = coreParams.FtqSize 747 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 748 def IntLogicRegs = coreParams.IntLogicRegs 749 def FpLogicRegs = coreParams.FpLogicRegs 750 def VecLogicRegs = coreParams.VecLogicRegs 751 def V0LogicRegs = coreParams.V0LogicRegs 752 def VlLogicRegs = coreParams.VlLogicRegs 753 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 754 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 755 def V0_IDX = coreParams.V0_IDX 756 def Vl_IDX = coreParams.Vl_IDX 757 def IntPhyRegs = coreParams.intPreg.numEntries 758 def FpPhyRegs = coreParams.fpPreg.numEntries 759 def VfPhyRegs = coreParams.vfPreg.numEntries 760 def V0PhyRegs = coreParams.v0Preg.numEntries 761 def VlPhyRegs = coreParams.vlPreg.numEntries 762 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 763 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 764 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 765 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 766 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 767 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 768 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 769 def RobSize = coreParams.RobSize 770 def RabSize = coreParams.RabSize 771 def VTypeBufferSize = coreParams.VTypeBufferSize 772 def IntRegCacheSize = coreParams.IntRegCacheSize 773 def MemRegCacheSize = coreParams.MemRegCacheSize 774 def RegCacheSize = coreParams.RegCacheSize 775 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 776 /** 777 * the minimum element length of vector elements 778 */ 779 def minVecElen: Int = coreParams.minVecElen 780 781 /** 782 * the maximum number of elements in vector register 783 */ 784 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 785 786 def IntRefCounterWidth = log2Ceil(RobSize) 787 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 788 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 789 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 790 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 791 def LoadQueueRARSize = coreParams.LoadQueueRARSize 792 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 793 def RollbackGroupSize = coreParams.RollbackGroupSize 794 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 795 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 796 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 797 def StoreQueueSize = coreParams.StoreQueueSize 798 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 799 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 800 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 801 def VlsQueueSize = coreParams.VlsQueueSize 802 def dpParams = coreParams.dpParams 803 804 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 805 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 806 807 def NumRedirect = backendParams.numRedirect 808 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 809 def FtqRedirectAheadNum = NumRedirect 810 def IfuRedirectNum = coreParams.IfuRedirectNum 811 def LoadPipelineWidth = coreParams.LoadPipelineWidth 812 def StorePipelineWidth = coreParams.StorePipelineWidth 813 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 814 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 815 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 816 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 817 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 818 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 819 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 820 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 821 def StoreBufferSize = coreParams.StoreBufferSize 822 def StoreBufferThreshold = coreParams.StoreBufferThreshold 823 def EnsbufferWidth = coreParams.EnsbufferWidth 824 def LoadDependencyWidth = coreParams.LoadDependencyWidth 825 def VlMergeBufferSize = coreParams.VlMergeBufferSize 826 def VsMergeBufferSize = coreParams.VsMergeBufferSize 827 def UopWritebackWidth = coreParams.UopWritebackWidth 828 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 829 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 830 def VSegmentBufferSize = coreParams.VSegmentBufferSize 831 def VFOFBufferSize = coreParams.VFOFBufferSize 832 def UncacheBufferSize = coreParams.UncacheBufferSize 833 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 834 def EnableFastForward = coreParams.EnableFastForward 835 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 836 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 837 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 838 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 839 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 840 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 841 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 842 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 843 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 844 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 845 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 846 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 847 def HasCMO = coreParams.HasCMO && p(EnableCHI) 848 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 849 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 850 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 851 def asidLen = coreParams.MMUAsidLen 852 def vmidLen = coreParams.MMUVmidLen 853 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 854 def refillBothTlb = coreParams.refillBothTlb 855 def iwpuParam = coreParams.iwpuParameters 856 def dwpuParam = coreParams.dwpuParameters 857 def itlbParams = coreParams.itlbParameters 858 def ldtlbParams = coreParams.ldtlbParameters 859 def sttlbParams = coreParams.sttlbParameters 860 def hytlbParams = coreParams.hytlbParameters 861 def pftlbParams = coreParams.pftlbParameters 862 def l2ToL1Params = coreParams.l2ToL1tlbParameters 863 def btlbParams = coreParams.btlbParameters 864 def l2tlbParams = coreParams.l2tlbParameters 865 def NumPerfCounters = coreParams.NumPerfCounters 866 867 def instBytes = if (HasCExtension) 2 else 4 868 def instOffsetBits = log2Ceil(instBytes) 869 870 def icacheParameters = coreParams.icacheParameters 871 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 872 873 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 874 // for constrained LR/SC loop 875 def LRSCCycles = 64 876 // for lr storm 877 def LRSCBackOff = 8 878 879 // cache hierarchy configurations 880 def l1BusDataWidth = 256 881 882 // load violation predict 883 def ResetTimeMax2Pow = 20 //1078576 884 def ResetTimeMin2Pow = 10 //1024 885 // wait table parameters 886 def WaitTableSize = 1024 887 def MemPredPCWidth = log2Up(WaitTableSize) 888 def LWTUse2BitCounter = true 889 // store set parameters 890 def SSITSize = WaitTableSize 891 def LFSTSize = 32 892 def SSIDWidth = log2Up(LFSTSize) 893 def LFSTWidth = 4 894 def StoreSetEnable = true // LWT will be disabled if SS is enabled 895 def LFSTEnable = true 896 897 def PCntIncrStep: Int = 6 898 def numPCntHc: Int = 12 899 def numPCntPtw: Int = 19 900 901 def numCSRPCntFrontend = 8 902 def numCSRPCntCtrl = 8 903 def numCSRPCntLsu = 8 904 def numCSRPCntHc = 5 905 def printEventCoding = true 906 def printCriticalError = false 907 def maxCommitStuck = pow(2, 21).toInt 908 909 // Vector load exception 910 def maxMergeNumPerCycle = 4 911 912 // Parameters for Sdtrig extension 913 protected def TriggerNum = 4 914 protected def TriggerChainMaxLength = 2 915 916 // Parameters for Trace extension 917 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 918 def CauseWidth = XLEN 919 def TvalWidth = coreParams.traceParams.IaddrWidth 920 def PrivWidth = coreParams.traceParams.PrivWidth 921 def IaddrWidth = coreParams.traceParams.IaddrWidth 922 def ItypeWidth = coreParams.traceParams.ItypeWidth 923 def IretireWidthInPipe = log2Up(RenameWidth * 2) 924 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 925 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 926} 927