1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 129 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 130 131 uftb.io.in.bits.resp_in(0) := resp_in 132 tage.io.in.bits.resp_in(0) := uftb.io.out 133 ftb.io.in.bits.resp_in(0) := tage.io.out 134 ittage.io.in.bits.resp_in(0) := ftb.io.out 135 ras.io.in.bits.resp_in(0) := ittage.io.out 136 137 (preds, ras.io.out) 138 }, 139 ICacheECCForceError: Boolean = false, 140 IBufSize: Int = 48, 141 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 8, 145 RobCommitWidth: Int = 8, 146 RabCommitWidth: Int = 6, 147 MaxUopSize: Int = 65, 148 EnableRenameSnapshot: Boolean = true, 149 RenameSnapshotNum: Int = 4, 150 FtqSize: Int = 64, 151 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 152 IntLogicRegs: Int = 32, 153 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 154 VecLogicRegs: Int = 32 + 15, // 15: tmp 155 V0LogicRegs: Int = 1, // V0 156 VlLogicRegs: Int = 1, // Vl 157 V0_IDX: Int = 0, 158 Vl_IDX: Int = 0, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 8, 181 FpDqDeqWidth = 6, 182 VecDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 fpPreg: PregParams = FpPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 vfPreg: VfPregParams = VfPregParams( 196 numEntries = 128, 197 numRead = None, 198 numWrite = None, 199 ), 200 v0Preg: V0PregParams = V0PregParams( 201 numEntries = 22, 202 numRead = None, 203 numWrite = None, 204 ), 205 vlPreg: VlPregParams = VlPregParams( 206 numEntries = 32, 207 numRead = None, 208 numWrite = None, 209 ), 210 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 211 LoadPipelineWidth: Int = 3, 212 StorePipelineWidth: Int = 2, 213 VecLoadPipelineWidth: Int = 2, 214 VecStorePipelineWidth: Int = 2, 215 VecMemSrcInWidth: Int = 2, 216 VecMemInstWbWidth: Int = 1, 217 VecMemDispatchWidth: Int = 1, 218 VecMemDispatchMaxNumber: Int = 16, 219 StoreBufferSize: Int = 16, 220 StoreBufferThreshold: Int = 7, 221 EnsbufferWidth: Int = 2, 222 LoadDependencyWidth: Int = 2, 223 // ============ VLSU ============ 224 VlMergeBufferSize: Int = 16, 225 VsMergeBufferSize: Int = 16, 226 UopWritebackWidth: Int = 2, 227 VLUopWritebackWidth: Int = 2, 228 VSUopWritebackWidth: Int = 1, 229 SplitBufferSize: Int = 8, 230 VSegmentBufferSize: Int = 8, 231 // ============================== 232 UncacheBufferSize: Int = 4, 233 EnableLoadToLoadForward: Boolean = false, 234 EnableFastForward: Boolean = true, 235 EnableLdVioCheckAfterReset: Boolean = true, 236 EnableSoftPrefetchAfterReset: Boolean = true, 237 EnableCacheErrorAfterReset: Boolean = true, 238 EnableAccurateLoadError: Boolean = false, 239 EnableUncacheWriteOutstanding: Boolean = false, 240 EnableStorePrefetchAtIssue: Boolean = false, 241 EnableStorePrefetchAtCommit: Boolean = false, 242 EnableAtCommitMissTrigger: Boolean = true, 243 EnableStorePrefetchSMS: Boolean = false, 244 EnableStorePrefetchSPB: Boolean = false, 245 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 246 MMUVmidLen: Int = 14, 247 ReSelectLen: Int = 7, // load replay queue replay select counter len 248 iwpuParameters: WPUParameters = WPUParameters( 249 enWPU = false, 250 algoName = "mmru", 251 isICache = true, 252 ), 253 dwpuParameters: WPUParameters = WPUParameters( 254 enWPU = false, 255 algoName = "mmru", 256 enCfPred = false, 257 isICache = false, 258 ), 259 itlbParameters: TLBParameters = TLBParameters( 260 name = "itlb", 261 fetchi = true, 262 useDmode = false, 263 NWays = 48, 264 ), 265 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 266 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 267 ldtlbParameters: TLBParameters = TLBParameters( 268 name = "ldtlb", 269 NWays = 48, 270 outReplace = false, 271 partialStaticPMP = true, 272 outsideRecvFlush = true, 273 saveLevel = true, 274 lgMaxSize = 4 275 ), 276 sttlbParameters: TLBParameters = TLBParameters( 277 name = "sttlb", 278 NWays = 48, 279 outReplace = false, 280 partialStaticPMP = true, 281 outsideRecvFlush = true, 282 saveLevel = true, 283 lgMaxSize = 4 284 ), 285 hytlbParameters: TLBParameters = TLBParameters( 286 name = "hytlb", 287 NWays = 48, 288 outReplace = false, 289 partialStaticPMP = true, 290 outsideRecvFlush = true, 291 saveLevel = true, 292 lgMaxSize = 4 293 ), 294 pftlbParameters: TLBParameters = TLBParameters( 295 name = "pftlb", 296 NWays = 48, 297 outReplace = false, 298 partialStaticPMP = true, 299 outsideRecvFlush = true, 300 saveLevel = true, 301 lgMaxSize = 4 302 ), 303 l2ToL1tlbParameters: TLBParameters = TLBParameters( 304 name = "l2tlb", 305 NWays = 48, 306 outReplace = false, 307 partialStaticPMP = true, 308 outsideRecvFlush = true, 309 saveLevel = true 310 ), 311 refillBothTlb: Boolean = false, 312 btlbParameters: TLBParameters = TLBParameters( 313 name = "btlb", 314 NWays = 48, 315 ), 316 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 317 NumPerfCounters: Int = 16, 318 icacheParameters: ICacheParameters = ICacheParameters( 319 tagECC = Some("parity"), 320 dataECC = Some("parity"), 321 replacer = Some("setplru"), 322 nMissEntries = 2, 323 nProbeEntries = 2, 324 nPrefetchEntries = 12, 325 nPrefBufferEntries = 32, 326 ), 327 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 328 tagECC = Some("secded"), 329 dataECC = Some("secded"), 330 replacer = Some("setplru"), 331 nMissEntries = 16, 332 nProbeEntries = 8, 333 nReleaseEntries = 18, 334 nMaxPrefetchEntry = 6, 335 )), 336 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 337 name = "l2", 338 ways = 8, 339 sets = 1024, // default 512KB L2 340 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 341 coupledL2.prefetch.TPParameters()), 342 )), 343 L2NBanks: Int = 1, 344 usePTWRepeater: Boolean = false, 345 softTLB: Boolean = false, // dpi-c l1tlb debug only 346 softPTW: Boolean = false, // dpi-c l2tlb debug only 347 softPTWDelay: Int = 1 348){ 349 def vlWidth = log2Up(VLEN) + 1 350 351 /** 352 * the minimum element length of vector elements 353 */ 354 val minVecElen: Int = 8 355 356 /** 357 * the maximum number of elements in vector register 358 */ 359 val maxElemPerVreg: Int = VLEN / minVecElen 360 361 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 362 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 363 364 val intSchdParams = { 365 implicit val schdType: SchedulerType = IntScheduler() 366 SchdBlockParams(Seq( 367 IssueBlockParams(Seq( 368 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 369 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 370 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 371 IssueBlockParams(Seq( 372 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 373 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 374 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 375 IssueBlockParams(Seq( 376 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 377 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 378 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 379 IssueBlockParams(Seq( 380 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 381 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 382 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 383 ), 384 numPregs = intPreg.numEntries, 385 numDeqOutside = 0, 386 schdType = schdType, 387 rfDataWidth = intPreg.dataCfg.dataWidth, 388 numUopIn = dpParams.IntDqDeqWidth, 389 ) 390 } 391 392 val fpSchdParams = { 393 implicit val schdType: SchedulerType = FpScheduler() 394 SchdBlockParams(Seq( 395 IssueBlockParams(Seq( 396 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 397 ), numEntries = 18, numEnq = 2, numComp = 16), 398 IssueBlockParams(Seq( 399 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 400 ), numEntries = 18, numEnq = 2, numComp = 16), 401 IssueBlockParams(Seq( 402 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 403 ), numEntries = 18, numEnq = 2, numComp = 16), 404 IssueBlockParams(Seq( 405 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 406 ), numEntries = 18, numEnq = 2, numComp = 16), 407 IssueBlockParams(Seq( 408 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 409 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 410 ), numEntries = 18, numEnq = 2, numComp = 16), 411 ), 412 numPregs = fpPreg.numEntries, 413 numDeqOutside = 0, 414 schdType = schdType, 415 rfDataWidth = fpPreg.dataCfg.dataWidth, 416 numUopIn = dpParams.VecDqDeqWidth, 417 ) 418 } 419 420 val vfSchdParams = { 421 implicit val schdType: SchedulerType = VfScheduler() 422 SchdBlockParams(Seq( 423 IssueBlockParams(Seq( 424 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 425 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 426 ), numEntries = 16, numEnq = 2, numComp = 14), 427 IssueBlockParams(Seq( 428 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 429 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 430 ), numEntries = 16, numEnq = 2, numComp = 14), 431 IssueBlockParams(Seq( 432 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 433 ), numEntries = 10, numEnq = 2, numComp = 8), 434 ), 435 numPregs = vfPreg.numEntries, 436 numDeqOutside = 0, 437 schdType = schdType, 438 rfDataWidth = vfPreg.dataCfg.dataWidth, 439 numUopIn = dpParams.VecDqDeqWidth, 440 ) 441 } 442 443 val memSchdParams = { 444 implicit val schdType: SchedulerType = MemScheduler() 445 val rfDataWidth = 64 446 447 SchdBlockParams(Seq( 448 IssueBlockParams(Seq( 449 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 450 ), numEntries = 16, numEnq = 2, numComp = 14), 451 IssueBlockParams(Seq( 452 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 453 ), numEntries = 16, numEnq = 2, numComp = 14), 454 IssueBlockParams(Seq( 455 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 456 ), numEntries = 16, numEnq = 2, numComp = 14), 457 IssueBlockParams(Seq( 458 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 459 ), numEntries = 16, numEnq = 2, numComp = 14), 460 IssueBlockParams(Seq( 461 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 462 ), numEntries = 16, numEnq = 2, numComp = 14), 463 IssueBlockParams(Seq( 464 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 465 ), numEntries = 16, numEnq = 2, numComp = 14), 466 IssueBlockParams(Seq( 467 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 468 ), numEntries = 16, numEnq = 2, numComp = 14), 469 IssueBlockParams(Seq( 470 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 471 ), numEntries = 16, numEnq = 2, numComp = 14), 472 IssueBlockParams(Seq( 473 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 474 ), numEntries = 16, numEnq = 2, numComp = 14), 475 ), 476 numPregs = intPreg.numEntries max vfPreg.numEntries, 477 numDeqOutside = 0, 478 schdType = schdType, 479 rfDataWidth = rfDataWidth, 480 numUopIn = dpParams.LsDqDeqWidth, 481 ) 482 } 483 484 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 485 486 def iqWakeUpParams = { 487 Seq( 488 WakeUpConfig( 489 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 490 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 491 ), 492 WakeUpConfig( 493 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 494 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 495 ), 496 WakeUpConfig( 497 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 498 Seq("STD0", "STD1") 499 ), 500 WakeUpConfig( 501 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 502 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 503 ), 504 ).flatten 505 } 506 507 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 508 509 val backendParams: BackendParams = backend.BackendParams( 510 Map( 511 IntScheduler() -> intSchdParams, 512 FpScheduler() -> fpSchdParams, 513 VfScheduler() -> vfSchdParams, 514 MemScheduler() -> memSchdParams, 515 ), 516 Seq( 517 intPreg, 518 fpPreg, 519 vfPreg, 520 v0Preg, 521 vlPreg, 522 fakeIntPreg 523 ), 524 iqWakeUpParams, 525 ) 526} 527 528case object DebugOptionsKey extends Field[DebugOptions] 529 530case class DebugOptions 531( 532 FPGAPlatform: Boolean = false, 533 ResetGen: Boolean = false, 534 EnableDifftest: Boolean = false, 535 AlwaysBasicDiff: Boolean = true, 536 EnableDebug: Boolean = false, 537 EnablePerfDebug: Boolean = true, 538 UseDRAMSim: Boolean = false, 539 EnableConstantin: Boolean = false, 540 EnableChiselDB: Boolean = false, 541 AlwaysBasicDB: Boolean = true, 542 EnableTopDown: Boolean = false, 543 EnableRollingDB: Boolean = false 544) 545 546trait HasXSParameter { 547 548 implicit val p: Parameters 549 550 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 551 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 552 553 def coreParams = p(XSCoreParamsKey) 554 def env = p(DebugOptionsKey) 555 556 def XLEN = coreParams.XLEN 557 def VLEN = coreParams.VLEN 558 def ELEN = coreParams.ELEN 559 def HSXLEN = coreParams.HSXLEN 560 val minFLen = 32 561 val fLen = 64 562 def hartIdLen = p(MaxHartIdBits) 563 val xLen = XLEN 564 565 def HasMExtension = coreParams.HasMExtension 566 def HasCExtension = coreParams.HasCExtension 567 def HasHExtension = coreParams.HasHExtension 568 def HasDiv = coreParams.HasDiv 569 def HasIcache = coreParams.HasICache 570 def HasDcache = coreParams.HasDCache 571 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 572 def GPAddrBits = coreParams.GPAddrBits 573 def VAddrBits = { 574 if(HasHExtension){ 575 coreParams.GPAddrBits 576 }else{ 577 coreParams.VAddrBits 578 } 579 } // VAddrBits is Virtual Memory addr bits 580 581 def AsidLength = coreParams.AsidLength 582 def VmidLength = coreParams.VmidLength 583 def ReSelectLen = coreParams.ReSelectLen 584 def AddrBytes = AddrBits / 8 // unused 585 def DataBits = XLEN 586 def DataBytes = DataBits / 8 587 def VDataBytes = VLEN / 8 588 def HasFPU = coreParams.HasFPU 589 def HasVPU = coreParams.HasVPU 590 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 591 def FetchWidth = coreParams.FetchWidth 592 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 593 def EnableBPU = coreParams.EnableBPU 594 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 595 def EnableRAS = coreParams.EnableRAS 596 def EnableLB = coreParams.EnableLB 597 def EnableLoop = coreParams.EnableLoop 598 def EnableSC = coreParams.EnableSC 599 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 600 def HistoryLength = coreParams.HistoryLength 601 def EnableGHistDiff = coreParams.EnableGHistDiff 602 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 603 def EnableClockGate = coreParams.EnableClockGate 604 def UbtbGHRLength = coreParams.UbtbGHRLength 605 def UbtbSize = coreParams.UbtbSize 606 def EnableFauFTB = coreParams.EnableFauFTB 607 def FtbSize = coreParams.FtbSize 608 def FtbWays = coreParams.FtbWays 609 def RasSize = coreParams.RasSize 610 def RasSpecSize = coreParams.RasSpecSize 611 def RasCtrSize = coreParams.RasCtrSize 612 613 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 614 coreParams.branchPredictor(resp_in, p) 615 } 616 def numBr = coreParams.numBr 617 def TageTableInfos = coreParams.TageTableInfos 618 def TageBanks = coreParams.numBr 619 def SCNRows = coreParams.SCNRows 620 def SCCtrBits = coreParams.SCCtrBits 621 def SCHistLens = coreParams.SCHistLens 622 def SCNTables = coreParams.SCNTables 623 624 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 625 case ((n, cb), h) => (n, cb, h) 626 } 627 def ITTageTableInfos = coreParams.ITTageTableInfos 628 type FoldedHistoryInfo = Tuple2[Int, Int] 629 def foldedGHistInfos = 630 (TageTableInfos.map{ case (nRows, h, t) => 631 if (h > 0) 632 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 633 else 634 Set[FoldedHistoryInfo]() 635 }.reduce(_++_).toSet ++ 636 SCTableInfos.map{ case (nRows, _, h) => 637 if (h > 0) 638 Set((h, min(log2Ceil(nRows/TageBanks), h))) 639 else 640 Set[FoldedHistoryInfo]() 641 }.reduce(_++_).toSet ++ 642 ITTageTableInfos.map{ case (nRows, h, t) => 643 if (h > 0) 644 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 645 else 646 Set[FoldedHistoryInfo]() 647 }.reduce(_++_) ++ 648 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 649 ).toList 650 651 652 653 def CacheLineSize = coreParams.CacheLineSize 654 def CacheLineHalfWord = CacheLineSize / 16 655 def ExtHistoryLength = HistoryLength + 64 656 def ICacheECCForceError = coreParams.ICacheECCForceError 657 def IBufSize = coreParams.IBufSize 658 def IBufNBank = coreParams.IBufNBank 659 def backendParams: BackendParams = coreParams.backendParams 660 def DecodeWidth = coreParams.DecodeWidth 661 def RenameWidth = coreParams.RenameWidth 662 def CommitWidth = coreParams.CommitWidth 663 def RobCommitWidth = coreParams.RobCommitWidth 664 def RabCommitWidth = coreParams.RabCommitWidth 665 def MaxUopSize = coreParams.MaxUopSize 666 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 667 def RenameSnapshotNum = coreParams.RenameSnapshotNum 668 def FtqSize = coreParams.FtqSize 669 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 670 def IntLogicRegs = coreParams.IntLogicRegs 671 def FpLogicRegs = coreParams.FpLogicRegs 672 def VecLogicRegs = coreParams.VecLogicRegs 673 def V0LogicRegs = coreParams.V0LogicRegs 674 def VlLogicRegs = coreParams.VlLogicRegs 675 def V0_IDX = coreParams.V0_IDX 676 def Vl_IDX = coreParams.Vl_IDX 677 def IntPhyRegs = coreParams.intPreg.numEntries 678 def FpPhyRegs = coreParams.fpPreg.numEntries 679 def VfPhyRegs = coreParams.vfPreg.numEntries 680 def V0PhyRegs = coreParams.v0Preg.numEntries 681 def VlPhyRegs = coreParams.vlPreg.numEntries 682 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 683 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 684 def RobSize = coreParams.RobSize 685 def RabSize = coreParams.RabSize 686 def VTypeBufferSize = coreParams.VTypeBufferSize 687 /** 688 * the minimum element length of vector elements 689 */ 690 def minVecElen: Int = coreParams.minVecElen 691 692 /** 693 * the maximum number of elements in vector register 694 */ 695 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 696 697 def IntRefCounterWidth = log2Ceil(RobSize) 698 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 699 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 700 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 701 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 702 def LoadQueueRARSize = coreParams.LoadQueueRARSize 703 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 704 def RollbackGroupSize = coreParams.RollbackGroupSize 705 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 706 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 707 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 708 def StoreQueueSize = coreParams.StoreQueueSize 709 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 710 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 711 def VlsQueueSize = coreParams.VlsQueueSize 712 def dpParams = coreParams.dpParams 713 714 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 715 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 716 717 def NumRedirect = backendParams.numRedirect 718 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 719 def FtqRedirectAheadNum = NumRedirect 720 def LoadPipelineWidth = coreParams.LoadPipelineWidth 721 def StorePipelineWidth = coreParams.StorePipelineWidth 722 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 723 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 724 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 725 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 726 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 727 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 728 def StoreBufferSize = coreParams.StoreBufferSize 729 def StoreBufferThreshold = coreParams.StoreBufferThreshold 730 def EnsbufferWidth = coreParams.EnsbufferWidth 731 def LoadDependencyWidth = coreParams.LoadDependencyWidth 732 def VlMergeBufferSize = coreParams.VlMergeBufferSize 733 def VsMergeBufferSize = coreParams.VsMergeBufferSize 734 def UopWritebackWidth = coreParams.UopWritebackWidth 735 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 736 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 737 def SplitBufferSize = coreParams.SplitBufferSize 738 def VSegmentBufferSize = coreParams.VSegmentBufferSize 739 def UncacheBufferSize = coreParams.UncacheBufferSize 740 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 741 def EnableFastForward = coreParams.EnableFastForward 742 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 743 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 744 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 745 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 746 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 747 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 748 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 749 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 750 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 751 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 752 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 753 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 754 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 755 def asidLen = coreParams.MMUAsidLen 756 def vmidLen = coreParams.MMUVmidLen 757 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 758 def refillBothTlb = coreParams.refillBothTlb 759 def iwpuParam = coreParams.iwpuParameters 760 def dwpuParam = coreParams.dwpuParameters 761 def itlbParams = coreParams.itlbParameters 762 def ldtlbParams = coreParams.ldtlbParameters 763 def sttlbParams = coreParams.sttlbParameters 764 def hytlbParams = coreParams.hytlbParameters 765 def pftlbParams = coreParams.pftlbParameters 766 def l2ToL1Params = coreParams.l2ToL1tlbParameters 767 def btlbParams = coreParams.btlbParameters 768 def l2tlbParams = coreParams.l2tlbParameters 769 def NumPerfCounters = coreParams.NumPerfCounters 770 771 def instBytes = if (HasCExtension) 2 else 4 772 def instOffsetBits = log2Ceil(instBytes) 773 774 def icacheParameters = coreParams.icacheParameters 775 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 776 777 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 778 // for constrained LR/SC loop 779 def LRSCCycles = 64 780 // for lr storm 781 def LRSCBackOff = 8 782 783 // cache hierarchy configurations 784 def l1BusDataWidth = 256 785 786 // load violation predict 787 def ResetTimeMax2Pow = 20 //1078576 788 def ResetTimeMin2Pow = 10 //1024 789 // wait table parameters 790 def WaitTableSize = 1024 791 def MemPredPCWidth = log2Up(WaitTableSize) 792 def LWTUse2BitCounter = true 793 // store set parameters 794 def SSITSize = WaitTableSize 795 def LFSTSize = 32 796 def SSIDWidth = log2Up(LFSTSize) 797 def LFSTWidth = 4 798 def StoreSetEnable = true // LWT will be disabled if SS is enabled 799 def LFSTEnable = true 800 801 def PCntIncrStep: Int = 6 802 def numPCntHc: Int = 25 803 def numPCntPtw: Int = 19 804 805 def numCSRPCntFrontend = 8 806 def numCSRPCntCtrl = 8 807 def numCSRPCntLsu = 8 808 def numCSRPCntHc = 5 809 def printEventCoding = true 810 811 // Parameters for Sdtrig extension 812 protected def TriggerNum = 4 813 protected def TriggerChainMaxLength = 2 814} 815