1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 152 V0LogicRegs: Int = 1, // V0 153 VlLogicRegs: Int = 1 + 1, // Vl, VCompress 154 VCONFIG_IDX: Int = 32, 155 NRPhyRegs: Int = 192, 156 VirtualLoadQueueSize: Int = 72, 157 LoadQueueRARSize: Int = 72, 158 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 159 RollbackGroupSize: Int = 8, 160 LoadQueueReplaySize: Int = 72, 161 LoadUncacheBufferSize: Int = 20, 162 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 163 StoreQueueSize: Int = 64, 164 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 165 StoreQueueForwardWithMask: Boolean = true, 166 VlsQueueSize: Int = 8, 167 RobSize: Int = 160, 168 RabSize: Int = 256, 169 VTypeBufferSize: Int = 64, // used to reorder vtype 170 IssueQueueSize: Int = 24, 171 IssueQueueCompEntrySize: Int = 16, 172 dpParams: DispatchParameters = DispatchParameters( 173 IntDqSize = 16, 174 FpDqSize = 16, 175 LsDqSize = 18, 176 IntDqDeqWidth = 8, 177 FpDqDeqWidth = 6, 178 VecDqDeqWidth = 6, 179 LsDqDeqWidth = 6, 180 ), 181 intPreg: PregParams = IntPregParams( 182 numEntries = 224, 183 numRead = None, 184 numWrite = None, 185 ), 186 fpPreg: PregParams = FpPregParams( 187 numEntries = 192, 188 numRead = None, 189 numWrite = None, 190 ), 191 vfPreg: VfPregParams = VfPregParams( 192 numEntries = 128, 193 numRead = None, 194 numWrite = None, 195 ), 196 v0Preg: V0PregParams = V0PregParams( 197 numEntries = 22, 198 numRead = None, 199 numWrite = None, 200 ), 201 vlPreg: VlPregParams = VlPregParams( 202 numEntries = 32, 203 numRead = None, 204 numWrite = None, 205 ), 206 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 207 LoadPipelineWidth: Int = 3, 208 StorePipelineWidth: Int = 2, 209 VecLoadPipelineWidth: Int = 1, 210 VecStorePipelineWidth: Int = 1, 211 VecMemSrcInWidth: Int = 2, 212 VecMemInstWbWidth: Int = 1, 213 VecMemDispatchWidth: Int = 1, 214 VecMemDispatchMaxNumber: Int = 16, 215 StoreBufferSize: Int = 16, 216 StoreBufferThreshold: Int = 7, 217 EnsbufferWidth: Int = 2, 218 LoadDependencyWidth: Int = 2, 219 // ============ VLSU ============ 220 VlMergeBufferSize: Int = 16, 221 VsMergeBufferSize: Int = 16, 222 UopWritebackWidth: Int = 1, 223 VLUopWritebackWidth: Int = 1, 224 VSUopWritebackWidth: Int = 1, 225 SplitBufferSize: Int = 8, 226 VSegmentBufferSize: Int = 8, 227 // ============================== 228 UncacheBufferSize: Int = 4, 229 EnableLoadToLoadForward: Boolean = false, 230 EnableFastForward: Boolean = true, 231 EnableLdVioCheckAfterReset: Boolean = true, 232 EnableSoftPrefetchAfterReset: Boolean = true, 233 EnableCacheErrorAfterReset: Boolean = true, 234 EnableAccurateLoadError: Boolean = true, 235 EnableUncacheWriteOutstanding: Boolean = false, 236 EnableStorePrefetchAtIssue: Boolean = false, 237 EnableStorePrefetchAtCommit: Boolean = false, 238 EnableAtCommitMissTrigger: Boolean = true, 239 EnableStorePrefetchSMS: Boolean = false, 240 EnableStorePrefetchSPB: Boolean = false, 241 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 242 MMUVmidLen: Int = 14, 243 ReSelectLen: Int = 7, // load replay queue replay select counter len 244 iwpuParameters: WPUParameters = WPUParameters( 245 enWPU = false, 246 algoName = "mmru", 247 isICache = true, 248 ), 249 dwpuParameters: WPUParameters = WPUParameters( 250 enWPU = false, 251 algoName = "mmru", 252 enCfPred = false, 253 isICache = false, 254 ), 255 itlbParameters: TLBParameters = TLBParameters( 256 name = "itlb", 257 fetchi = true, 258 useDmode = false, 259 NWays = 48, 260 ), 261 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 262 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 263 ldtlbParameters: TLBParameters = TLBParameters( 264 name = "ldtlb", 265 NWays = 48, 266 outReplace = false, 267 partialStaticPMP = true, 268 outsideRecvFlush = true, 269 saveLevel = true, 270 lgMaxSize = 4 271 ), 272 sttlbParameters: TLBParameters = TLBParameters( 273 name = "sttlb", 274 NWays = 48, 275 outReplace = false, 276 partialStaticPMP = true, 277 outsideRecvFlush = true, 278 saveLevel = true, 279 lgMaxSize = 4 280 ), 281 hytlbParameters: TLBParameters = TLBParameters( 282 name = "hytlb", 283 NWays = 48, 284 outReplace = false, 285 partialStaticPMP = true, 286 outsideRecvFlush = true, 287 saveLevel = true, 288 lgMaxSize = 4 289 ), 290 pftlbParameters: TLBParameters = TLBParameters( 291 name = "pftlb", 292 NWays = 48, 293 outReplace = false, 294 partialStaticPMP = true, 295 outsideRecvFlush = true, 296 saveLevel = true, 297 lgMaxSize = 4 298 ), 299 l2ToL1tlbParameters: TLBParameters = TLBParameters( 300 name = "l2tlb", 301 NWays = 48, 302 outReplace = false, 303 partialStaticPMP = true, 304 outsideRecvFlush = true, 305 saveLevel = true 306 ), 307 refillBothTlb: Boolean = false, 308 btlbParameters: TLBParameters = TLBParameters( 309 name = "btlb", 310 NWays = 48, 311 ), 312 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 313 NumPerfCounters: Int = 16, 314 icacheParameters: ICacheParameters = ICacheParameters( 315 tagECC = Some("parity"), 316 dataECC = Some("parity"), 317 replacer = Some("setplru"), 318 nMissEntries = 2, 319 nProbeEntries = 2, 320 nPrefetchEntries = 12, 321 nPrefBufferEntries = 32, 322 ), 323 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 324 tagECC = Some("secded"), 325 dataECC = Some("secded"), 326 replacer = Some("setplru"), 327 nMissEntries = 16, 328 nProbeEntries = 8, 329 nReleaseEntries = 18, 330 nMaxPrefetchEntry = 6, 331 )), 332 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 333 name = "l2", 334 ways = 8, 335 sets = 1024, // default 512KB L2 336 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 337 coupledL2.prefetch.TPParameters()), 338 )), 339 L2NBanks: Int = 1, 340 usePTWRepeater: Boolean = false, 341 softTLB: Boolean = false, // dpi-c l1tlb debug only 342 softPTW: Boolean = false, // dpi-c l2tlb debug only 343 softPTWDelay: Int = 1 344){ 345 def vlWidth = log2Up(VLEN) + 1 346 347 /** 348 * the minimum element length of vector elements 349 */ 350 val minVecElen: Int = 8 351 352 /** 353 * the maximum number of elements in vector register 354 */ 355 val maxElemPerVreg: Int = VLEN / minVecElen 356 357 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 358 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 359 360 val intSchdParams = { 361 implicit val schdType: SchedulerType = IntScheduler() 362 SchdBlockParams(Seq( 363 IssueBlockParams(Seq( 364 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 365 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 366 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 367 IssueBlockParams(Seq( 368 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 369 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 370 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 371 IssueBlockParams(Seq( 372 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 373 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 374 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 375 IssueBlockParams(Seq( 376 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 377 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 378 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 379 ), 380 numPregs = intPreg.numEntries, 381 numDeqOutside = 0, 382 schdType = schdType, 383 rfDataWidth = intPreg.dataCfg.dataWidth, 384 numUopIn = dpParams.IntDqDeqWidth, 385 ) 386 } 387 388 val fpSchdParams = { 389 implicit val schdType: SchedulerType = FpScheduler() 390 SchdBlockParams(Seq( 391 IssueBlockParams(Seq( 392 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 393 ), numEntries = 18, numEnq = 2, numComp = 16), 394 IssueBlockParams(Seq( 395 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 396 ), numEntries = 18, numEnq = 2, numComp = 16), 397 IssueBlockParams(Seq( 398 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 399 ), numEntries = 18, numEnq = 2, numComp = 16), 400 IssueBlockParams(Seq( 401 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 402 ), numEntries = 18, numEnq = 2, numComp = 16), 403 IssueBlockParams(Seq( 404 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 405 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 406 ), numEntries = 18, numEnq = 2, numComp = 16), 407 ), 408 numPregs = fpPreg.numEntries, 409 numDeqOutside = 0, 410 schdType = schdType, 411 rfDataWidth = fpPreg.dataCfg.dataWidth, 412 numUopIn = dpParams.VecDqDeqWidth, 413 ) 414 } 415 416 val vfSchdParams = { 417 implicit val schdType: SchedulerType = VfScheduler() 418 SchdBlockParams(Seq( 419 IssueBlockParams(Seq( 420 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 421 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(2, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 422 ), numEntries = 16, numEnq = 2, numComp = 14), 423 IssueBlockParams(Seq( 424 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 425 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 426 ), numEntries = 16, numEnq = 2, numComp = 14), 427 IssueBlockParams(Seq( 428 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 429 ), numEntries = 10, numEnq = 2, numComp = 8), 430 ), 431 numPregs = vfPreg.numEntries, 432 numDeqOutside = 0, 433 schdType = schdType, 434 rfDataWidth = vfPreg.dataCfg.dataWidth, 435 numUopIn = dpParams.VecDqDeqWidth, 436 ) 437 } 438 439 val memSchdParams = { 440 implicit val schdType: SchedulerType = MemScheduler() 441 val rfDataWidth = 64 442 443 SchdBlockParams(Seq( 444 IssueBlockParams(Seq( 445 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 446 ), numEntries = 16, numEnq = 2, numComp = 14), 447 IssueBlockParams(Seq( 448 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 449 ), numEntries = 16, numEnq = 2, numComp = 14), 450 IssueBlockParams(Seq( 451 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 452 ), numEntries = 16, numEnq = 2, numComp = 14), 453 IssueBlockParams(Seq( 454 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 455 ), numEntries = 16, numEnq = 2, numComp = 14), 456 IssueBlockParams(Seq( 457 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 458 ), numEntries = 16, numEnq = 2, numComp = 14), 459 IssueBlockParams(Seq( 460 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 461 ), numEntries = 16, numEnq = 2, numComp = 14), 462 IssueBlockParams(Seq( 463 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 464 ), numEntries = 16, numEnq = 2, numComp = 14), 465 IssueBlockParams(Seq( 466 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 467 ), numEntries = 16, numEnq = 2, numComp = 14), 468 IssueBlockParams(Seq( 469 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 470 ), numEntries = 16, numEnq = 2, numComp = 14), 471 ), 472 numPregs = intPreg.numEntries max vfPreg.numEntries, 473 numDeqOutside = 0, 474 schdType = schdType, 475 rfDataWidth = rfDataWidth, 476 numUopIn = dpParams.LsDqDeqWidth, 477 ) 478 } 479 480 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 481 482 def iqWakeUpParams = { 483 Seq( 484 WakeUpConfig( 485 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 486 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 487 ), 488 WakeUpConfig( 489 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 490 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 491 ), 492 WakeUpConfig( 493 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 494 Seq("STD0", "STD1") 495 ), 496 WakeUpConfig( 497 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 498 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 499 ), 500 ).flatten 501 } 502 503 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 504 505 val backendParams: BackendParams = backend.BackendParams( 506 Map( 507 IntScheduler() -> intSchdParams, 508 FpScheduler() -> fpSchdParams, 509 VfScheduler() -> vfSchdParams, 510 MemScheduler() -> memSchdParams, 511 ), 512 Seq( 513 intPreg, 514 fpPreg, 515 vfPreg, 516 v0Preg, 517 vlPreg, 518 fakeIntPreg 519 ), 520 iqWakeUpParams, 521 ) 522} 523 524case object DebugOptionsKey extends Field[DebugOptions] 525 526case class DebugOptions 527( 528 FPGAPlatform: Boolean = false, 529 ResetGen: Boolean = false, 530 EnableDifftest: Boolean = false, 531 AlwaysBasicDiff: Boolean = true, 532 EnableDebug: Boolean = false, 533 EnablePerfDebug: Boolean = true, 534 UseDRAMSim: Boolean = false, 535 EnableConstantin: Boolean = false, 536 EnableChiselDB: Boolean = false, 537 AlwaysBasicDB: Boolean = true, 538 EnableTopDown: Boolean = false, 539 EnableRollingDB: Boolean = false 540) 541 542trait HasXSParameter { 543 544 implicit val p: Parameters 545 546 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 547 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 548 549 def coreParams = p(XSCoreParamsKey) 550 def env = p(DebugOptionsKey) 551 552 def XLEN = coreParams.XLEN 553 def VLEN = coreParams.VLEN 554 def ELEN = coreParams.ELEN 555 def HSXLEN = coreParams.HSXLEN 556 val minFLen = 32 557 val fLen = 64 558 def hartIdLen = p(MaxHartIdBits) 559 val xLen = XLEN 560 561 def HasMExtension = coreParams.HasMExtension 562 def HasCExtension = coreParams.HasCExtension 563 def HasHExtension = coreParams.HasHExtension 564 def HasDiv = coreParams.HasDiv 565 def HasIcache = coreParams.HasICache 566 def HasDcache = coreParams.HasDCache 567 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 568 def GPAddrBits = coreParams.GPAddrBits 569 def VAddrBits = { 570 if(HasHExtension){ 571 coreParams.GPAddrBits 572 }else{ 573 coreParams.VAddrBits 574 } 575 } // VAddrBits is Virtual Memory addr bits 576 577 def AsidLength = coreParams.AsidLength 578 def VmidLength = coreParams.VmidLength 579 def ReSelectLen = coreParams.ReSelectLen 580 def AddrBytes = AddrBits / 8 // unused 581 def DataBits = XLEN 582 def DataBytes = DataBits / 8 583 def VDataBytes = VLEN / 8 584 def HasFPU = coreParams.HasFPU 585 def HasVPU = coreParams.HasVPU 586 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 587 def FetchWidth = coreParams.FetchWidth 588 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 589 def EnableBPU = coreParams.EnableBPU 590 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 591 def EnableRAS = coreParams.EnableRAS 592 def EnableLB = coreParams.EnableLB 593 def EnableLoop = coreParams.EnableLoop 594 def EnableSC = coreParams.EnableSC 595 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 596 def HistoryLength = coreParams.HistoryLength 597 def EnableGHistDiff = coreParams.EnableGHistDiff 598 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 599 def EnableClockGate = coreParams.EnableClockGate 600 def UbtbGHRLength = coreParams.UbtbGHRLength 601 def UbtbSize = coreParams.UbtbSize 602 def EnableFauFTB = coreParams.EnableFauFTB 603 def FtbSize = coreParams.FtbSize 604 def FtbWays = coreParams.FtbWays 605 def RasSize = coreParams.RasSize 606 def RasSpecSize = coreParams.RasSpecSize 607 def RasCtrSize = coreParams.RasCtrSize 608 609 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 610 coreParams.branchPredictor(resp_in, p) 611 } 612 def numBr = coreParams.numBr 613 def TageTableInfos = coreParams.TageTableInfos 614 def TageBanks = coreParams.numBr 615 def SCNRows = coreParams.SCNRows 616 def SCCtrBits = coreParams.SCCtrBits 617 def SCHistLens = coreParams.SCHistLens 618 def SCNTables = coreParams.SCNTables 619 620 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 621 case ((n, cb), h) => (n, cb, h) 622 } 623 def ITTageTableInfos = coreParams.ITTageTableInfos 624 type FoldedHistoryInfo = Tuple2[Int, Int] 625 def foldedGHistInfos = 626 (TageTableInfos.map{ case (nRows, h, t) => 627 if (h > 0) 628 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 629 else 630 Set[FoldedHistoryInfo]() 631 }.reduce(_++_).toSet ++ 632 SCTableInfos.map{ case (nRows, _, h) => 633 if (h > 0) 634 Set((h, min(log2Ceil(nRows/TageBanks), h))) 635 else 636 Set[FoldedHistoryInfo]() 637 }.reduce(_++_).toSet ++ 638 ITTageTableInfos.map{ case (nRows, h, t) => 639 if (h > 0) 640 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 641 else 642 Set[FoldedHistoryInfo]() 643 }.reduce(_++_) ++ 644 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 645 ).toList 646 647 648 649 def CacheLineSize = coreParams.CacheLineSize 650 def CacheLineHalfWord = CacheLineSize / 16 651 def ExtHistoryLength = HistoryLength + 64 652 def ICacheECCForceError = coreParams.ICacheECCForceError 653 def IBufSize = coreParams.IBufSize 654 def IBufNBank = coreParams.IBufNBank 655 def backendParams: BackendParams = coreParams.backendParams 656 def DecodeWidth = coreParams.DecodeWidth 657 def RenameWidth = coreParams.RenameWidth 658 def CommitWidth = coreParams.CommitWidth 659 def RobCommitWidth = coreParams.RobCommitWidth 660 def RabCommitWidth = coreParams.RabCommitWidth 661 def MaxUopSize = coreParams.MaxUopSize 662 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 663 def RenameSnapshotNum = coreParams.RenameSnapshotNum 664 def FtqSize = coreParams.FtqSize 665 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 666 def IntLogicRegs = coreParams.IntLogicRegs 667 def FpLogicRegs = coreParams.FpLogicRegs 668 def VecLogicRegs = coreParams.VecLogicRegs 669 def V0LogicRegs = coreParams.V0LogicRegs 670 def VlLogicRegs = coreParams.VlLogicRegs 671 def VCONFIG_IDX = coreParams.VCONFIG_IDX 672 def IntPhyRegs = coreParams.intPreg.numEntries 673 def FpPhyRegs = coreParams.fpPreg.numEntries 674 def VfPhyRegs = coreParams.vfPreg.numEntries 675 def V0PhyRegs = coreParams.v0Preg.numEntries 676 def VlPhyRegs = coreParams.vlPreg.numEntries 677 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 678 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 679 def RobSize = coreParams.RobSize 680 def RabSize = coreParams.RabSize 681 def VTypeBufferSize = coreParams.VTypeBufferSize 682 /** 683 * the minimum element length of vector elements 684 */ 685 def minVecElen: Int = coreParams.minVecElen 686 687 /** 688 * the maximum number of elements in vector register 689 */ 690 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 691 692 def IntRefCounterWidth = log2Ceil(RobSize) 693 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 694 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 695 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 696 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 697 def LoadQueueRARSize = coreParams.LoadQueueRARSize 698 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 699 def RollbackGroupSize = coreParams.RollbackGroupSize 700 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 701 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 702 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 703 def StoreQueueSize = coreParams.StoreQueueSize 704 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 705 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 706 def VlsQueueSize = coreParams.VlsQueueSize 707 def dpParams = coreParams.dpParams 708 709 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 710 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 711 712 def NumRedirect = backendParams.numRedirect 713 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 714 def FtqRedirectAheadNum = NumRedirect 715 def LoadPipelineWidth = coreParams.LoadPipelineWidth 716 def StorePipelineWidth = coreParams.StorePipelineWidth 717 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 718 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 719 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 720 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 721 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 722 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 723 def StoreBufferSize = coreParams.StoreBufferSize 724 def StoreBufferThreshold = coreParams.StoreBufferThreshold 725 def EnsbufferWidth = coreParams.EnsbufferWidth 726 def LoadDependencyWidth = coreParams.LoadDependencyWidth 727 def VlMergeBufferSize = coreParams.VlMergeBufferSize 728 def VsMergeBufferSize = coreParams.VsMergeBufferSize 729 def UopWritebackWidth = coreParams.UopWritebackWidth 730 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 731 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 732 def SplitBufferSize = coreParams.SplitBufferSize 733 def VSegmentBufferSize = coreParams.VSegmentBufferSize 734 def UncacheBufferSize = coreParams.UncacheBufferSize 735 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 736 def EnableFastForward = coreParams.EnableFastForward 737 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 738 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 739 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 740 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 741 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 742 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 743 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 744 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 745 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 746 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 747 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 748 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 749 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 750 def asidLen = coreParams.MMUAsidLen 751 def vmidLen = coreParams.MMUVmidLen 752 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 753 def refillBothTlb = coreParams.refillBothTlb 754 def iwpuParam = coreParams.iwpuParameters 755 def dwpuParam = coreParams.dwpuParameters 756 def itlbParams = coreParams.itlbParameters 757 def ldtlbParams = coreParams.ldtlbParameters 758 def sttlbParams = coreParams.sttlbParameters 759 def hytlbParams = coreParams.hytlbParameters 760 def pftlbParams = coreParams.pftlbParameters 761 def l2ToL1Params = coreParams.l2ToL1tlbParameters 762 def btlbParams = coreParams.btlbParameters 763 def l2tlbParams = coreParams.l2tlbParameters 764 def NumPerfCounters = coreParams.NumPerfCounters 765 766 def instBytes = if (HasCExtension) 2 else 4 767 def instOffsetBits = log2Ceil(instBytes) 768 769 def icacheParameters = coreParams.icacheParameters 770 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 771 772 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 773 // for constrained LR/SC loop 774 def LRSCCycles = 64 775 // for lr storm 776 def LRSCBackOff = 8 777 778 // cache hierarchy configurations 779 def l1BusDataWidth = 256 780 781 // load violation predict 782 def ResetTimeMax2Pow = 20 //1078576 783 def ResetTimeMin2Pow = 10 //1024 784 // wait table parameters 785 def WaitTableSize = 1024 786 def MemPredPCWidth = log2Up(WaitTableSize) 787 def LWTUse2BitCounter = true 788 // store set parameters 789 def SSITSize = WaitTableSize 790 def LFSTSize = 32 791 def SSIDWidth = log2Up(LFSTSize) 792 def LFSTWidth = 4 793 def StoreSetEnable = true // LWT will be disabled if SS is enabled 794 def LFSTEnable = true 795 796 def PCntIncrStep: Int = 6 797 def numPCntHc: Int = 25 798 def numPCntPtw: Int = 19 799 800 def numCSRPCntFrontend = 8 801 def numCSRPCntCtrl = 8 802 def numCSRPCntLsu = 8 803 def numCSRPCntHc = 5 804 def printEventCoding = true 805 806 // Parameters for Sdtrig extension 807 protected def TriggerNum = 4 808 protected def TriggerChainMaxLength = 2 809} 810