1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 HasCustomCSRCacheOp: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 32, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 val ittage = Module(new ITTage()(p)) 79 // val tage = Module(new Tage()(p)) 80 // val fake = Module(new FakePredictor()(p)) 81 82 // val preds = Seq(loop, tage, btb, ubtb, bim) 83 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 84 preds.map(_.io := DontCare) 85 86 // ubtb.io.resp_in(0) := resp_in 87 // bim.io.resp_in(0) := ubtb.io.resp 88 // btb.io.resp_in(0) := bim.io.resp 89 // tage.io.resp_in(0) := btb.io.resp 90 // loop.io.resp_in(0) := tage.io.resp 91 bim.io.in.bits.resp_in(0) := resp_in 92 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 93 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 94 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 95 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 96 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 97 98 (preds, ras.io.out.resp) 99 }), 100 IBufSize: Int = 48, 101 DecodeWidth: Int = 6, 102 RenameWidth: Int = 6, 103 CommitWidth: Int = 6, 104 FtqSize: Int = 64, 105 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 106 IssQueSize: Int = 16, 107 NRPhyRegs: Int = 192, 108 NRIntReadPorts: Int = 14, 109 NRIntWritePorts: Int = 8, 110 NRFpReadPorts: Int = 14, 111 NRFpWritePorts: Int = 8, 112 LoadQueueSize: Int = 80, 113 StoreQueueSize: Int = 64, 114 RobSize: Int = 256, 115 dpParams: DispatchParameters = DispatchParameters( 116 IntDqSize = 16, 117 FpDqSize = 16, 118 LsDqSize = 16, 119 IntDqDeqWidth = 4, 120 FpDqDeqWidth = 4, 121 LsDqDeqWidth = 4 122 ), 123 exuParameters: ExuParameters = ExuParameters( 124 JmpCnt = 1, 125 AluCnt = 4, 126 MulCnt = 0, 127 MduCnt = 2, 128 FmacCnt = 4, 129 FmiscCnt = 2, 130 FmiscDivSqrtCnt = 0, 131 LduCnt = 2, 132 StuCnt = 2 133 ), 134 LoadPipelineWidth: Int = 2, 135 StorePipelineWidth: Int = 2, 136 StoreBufferSize: Int = 16, 137 StoreBufferThreshold: Int = 7, 138 EnableFastForward: Boolean = true, 139 RefillSize: Int = 512, 140 itlbParameters: TLBParameters = TLBParameters( 141 name = "itlb", 142 fetchi = true, 143 useDmode = false, 144 sameCycle = true, 145 normalNWays = 32, 146 normalReplacer = Some("plru"), 147 superNWays = 4, 148 superReplacer = Some("plru"), 149 shouldBlock = true 150 ), 151 ldtlbParameters: TLBParameters = TLBParameters( 152 name = "ldtlb", 153 normalNSets = 128, 154 normalNWays = 1, 155 normalAssociative = "sa", 156 normalReplacer = Some("setplru"), 157 superNWays = 8, 158 normalAsVictim = true, 159 outReplace = true 160 ), 161 sttlbParameters: TLBParameters = TLBParameters( 162 name = "sttlb", 163 normalNSets = 128, 164 normalNWays = 1, 165 normalAssociative = "sa", 166 normalReplacer = Some("setplru"), 167 superNWays = 8, 168 normalAsVictim = true, 169 outReplace = true 170 ), 171 refillBothTlb: Boolean = false, 172 btlbParameters: TLBParameters = TLBParameters( 173 name = "btlb", 174 normalNSets = 1, 175 normalNWays = 64, 176 superNWays = 4, 177 ), 178 useBTlb: Boolean = false, 179 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 180 NumPMP: Int = 16, // 0 or 16 or 64 181 NumPerfCounters: Int = 16, 182 icacheParameters: ICacheParameters = ICacheParameters( 183 tagECC = Some("parity"), 184 dataECC = Some("parity"), 185 replacer = Some("setplru"), 186 nMissEntries = 2 187 ), 188 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 189 tagECC = Some("secded"), 190 dataECC = Some("secded"), 191 replacer = Some("setplru"), 192 nMissEntries = 16, 193 nProbeEntries = 16, 194 nReleaseEntries = 32 195 )), 196 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 197 name = "l2", 198 level = 2, 199 ways = 8, 200 sets = 1024, // default 512KB L2 201 prefetch = Some(huancun.prefetch.BOPParameters()) 202 )), 203 L2NBanks: Int = 1, 204 usePTWRepeater: Boolean = false, 205 softPTW: Boolean = false // dpi-c debug only 206){ 207 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 208 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 209 210 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 211 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 212 213 val fpExuConfigs = 214 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 215 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 216 217 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 218} 219 220case object DebugOptionsKey extends Field[DebugOptions] 221 222case class DebugOptions 223( 224 FPGAPlatform: Boolean = true, 225 EnableDebug: Boolean = true, 226 EnablePerfDebug: Boolean = true, 227 UseDRAMSim: Boolean = false 228) 229 230trait HasXSParameter { 231 232 implicit val p: Parameters 233 234 val coreParams = p(XSCoreParamsKey) 235 val env = p(DebugOptionsKey) 236 237 val XLEN = coreParams.XLEN 238 val hardId = coreParams.HartId 239 val minFLen = 32 240 val fLen = 64 241 def xLen = XLEN 242 243 val HasMExtension = coreParams.HasMExtension 244 val HasCExtension = coreParams.HasCExtension 245 val HasDiv = coreParams.HasDiv 246 val HasIcache = coreParams.HasICache 247 val HasDcache = coreParams.HasDCache 248 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 249 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 250 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 251 val AddrBytes = AddrBits / 8 // unused 252 val DataBits = XLEN 253 val DataBytes = DataBits / 8 254 val HasFPU = coreParams.HasFPU 255 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 256 val FetchWidth = coreParams.FetchWidth 257 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 258 val EnableBPU = coreParams.EnableBPU 259 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 260 val EnableRAS = coreParams.EnableRAS 261 val EnableLB = coreParams.EnableLB 262 val EnableLoop = coreParams.EnableLoop 263 val EnableSC = coreParams.EnableSC 264 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 265 val HistoryLength = coreParams.HistoryLength 266 val PathHistoryLength = coreParams.PathHistoryLength 267 val BtbSize = coreParams.BtbSize 268 // val BtbWays = 4 269 val BtbBanks = PredictWidth 270 // val BtbSets = BtbSize / BtbWays 271 val JbtacSize = coreParams.JbtacSize 272 val JbtacBanks = coreParams.JbtacBanks 273 val RasSize = coreParams.RasSize 274 275 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 276 coreParams.branchPredictor(resp_in, p, enableSC) 277 } 278 279 val CacheLineSize = coreParams.CacheLineSize 280 val CacheLineHalfWord = CacheLineSize / 16 281 val ExtHistoryLength = HistoryLength + 64 282 val UBtbWays = coreParams.UBtbWays 283 val BtbWays = coreParams.BtbWays 284 val IBufSize = coreParams.IBufSize 285 val DecodeWidth = coreParams.DecodeWidth 286 val RenameWidth = coreParams.RenameWidth 287 val CommitWidth = coreParams.CommitWidth 288 val FtqSize = coreParams.FtqSize 289 val IssQueSize = coreParams.IssQueSize 290 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 291 val NRPhyRegs = coreParams.NRPhyRegs 292 val PhyRegIdxWidth = log2Up(NRPhyRegs) 293 val RobSize = coreParams.RobSize 294 val IntRefCounterWidth = log2Ceil(RobSize) 295 val StdFreeListSize = NRPhyRegs - 32 296 val MEFreeListSize = NRPhyRegs 297 val LoadQueueSize = coreParams.LoadQueueSize 298 val StoreQueueSize = coreParams.StoreQueueSize 299 val dpParams = coreParams.dpParams 300 val exuParameters = coreParams.exuParameters 301 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 302 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 303 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 304 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 305 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 306 val LoadPipelineWidth = coreParams.LoadPipelineWidth 307 val StorePipelineWidth = coreParams.StorePipelineWidth 308 val StoreBufferSize = coreParams.StoreBufferSize 309 val StoreBufferThreshold = coreParams.StoreBufferThreshold 310 val EnableFastForward = coreParams.EnableFastForward 311 val RefillSize = coreParams.RefillSize 312 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 313 val refillBothTlb = coreParams.refillBothTlb 314 val useBTlb = coreParams.useBTlb 315 val itlbParams = coreParams.itlbParameters 316 val ldtlbParams = coreParams.ldtlbParameters 317 val sttlbParams = coreParams.sttlbParameters 318 val btlbParams = coreParams.btlbParameters 319 val l2tlbParams = coreParams.l2tlbParameters 320 val NumPMP = coreParams.NumPMP 321 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 322 val NumPerfCounters = coreParams.NumPerfCounters 323 324 val instBytes = if (HasCExtension) 2 else 4 325 val instOffsetBits = log2Ceil(instBytes) 326 327 val icacheParameters = coreParams.icacheParameters 328 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 329 330 val LRSCCycles = 100 331 332 // cache hierarchy configurations 333 val l1BusDataWidth = 256 334 335 // load violation predict 336 val ResetTimeMax2Pow = 20 //1078576 337 val ResetTimeMin2Pow = 10 //1024 338 // wait table parameters 339 val WaitTableSize = 1024 340 val MemPredPCWidth = log2Up(WaitTableSize) 341 val LWTUse2BitCounter = true 342 // store set parameters 343 val SSITSize = WaitTableSize 344 val LFSTSize = 32 345 val SSIDWidth = log2Up(LFSTSize) 346 val LFSTWidth = 4 347 val StoreSetEnable = true // LWT will be disabled if SS is enabled 348 349 val loadExuConfigs = coreParams.loadExuConfigs 350 val storeExuConfigs = coreParams.storeExuConfigs 351 352 val intExuConfigs = coreParams.intExuConfigs 353 354 val fpExuConfigs = coreParams.fpExuConfigs 355 356 val exuConfigs = coreParams.exuConfigs 357 358} 359