xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision ac4d321d18df4775b9ddda83e77cf526a0b1ca67) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import huancun._
23import system.SoCParamsKey
24import xiangshan.backend.datapath.RdConfig._
25import xiangshan.backend.datapath.WbConfig._
26import xiangshan.backend.dispatch.DispatchParameters
27import xiangshan.backend.exu.ExeUnitParams
28import xiangshan.backend.fu.FuConfig._
29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler}
30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams}
31import xiangshan.backend.BackendParams
32import xiangshan.cache.DCacheParameters
33import xiangshan.cache.prefetch._
34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB}
35import xiangshan.frontend.icache.ICacheParameters
36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
37import xiangshan.frontend._
38import xiangshan.frontend.icache.ICacheParameters
39
40import freechips.rocketchip.diplomacy.AddressSet
41import freechips.rocketchip.tile.MaxHartIdBits
42import system.SoCParamsKey
43import huancun._
44import huancun.debug._
45import xiangshan.cache.wpu.WPUParameters
46import coupledL2._
47import xiangshan.backend.datapath.WakeUpConfig
48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams}
49
50import scala.math.min
51
52case object XSTileKey extends Field[Seq[XSCoreParameters]]
53
54case object XSCoreParamsKey extends Field[XSCoreParameters]
55
56case class XSCoreParameters
57(
58  HasPrefetch: Boolean = false,
59  HartId: Int = 0,
60  XLEN: Int = 64,
61  VLEN: Int = 128,
62  ELEN: Int = 64,
63  HSXLEN: Int = 64,
64  HasMExtension: Boolean = true,
65  HasCExtension: Boolean = true,
66  HasHExtension: Boolean = true,
67  HasDiv: Boolean = true,
68  HasICache: Boolean = true,
69  HasDCache: Boolean = true,
70  AddrBits: Int = 64,
71  VAddrBits: Int = 39,
72  GPAddrBits: Int = 41,
73  HasFPU: Boolean = true,
74  HasVPU: Boolean = true,
75  HasCustomCSRCacheOp: Boolean = true,
76  FetchWidth: Int = 8,
77  AsidLength: Int = 16,
78  VmidLength: Int = 14,
79  EnableBPU: Boolean = true,
80  EnableBPD: Boolean = true,
81  EnableRAS: Boolean = true,
82  EnableLB: Boolean = false,
83  EnableLoop: Boolean = true,
84  EnableSC: Boolean = true,
85  EnbaleTlbDebug: Boolean = false,
86  EnableClockGate: Boolean = true,
87  EnableJal: Boolean = false,
88  EnableFauFTB: Boolean = true,
89  UbtbGHRLength: Int = 4,
90  // HistoryLength: Int = 512,
91  EnableGHistDiff: Boolean = true,
92  EnableCommitGHistDiff: Boolean = true,
93  UbtbSize: Int = 256,
94  FtbSize: Int = 2048,
95  RasSize: Int = 16,
96  RasSpecSize: Int = 32,
97  RasCtrSize: Int = 3,
98  CacheLineSize: Int = 512,
99  FtbWays: Int = 4,
100  TageTableInfos: Seq[Tuple3[Int,Int,Int]] =
101  //       Sets  Hist   Tag
102    // Seq(( 2048,    2,    8),
103    //     ( 2048,    9,    8),
104    //     ( 2048,   13,    8),
105    //     ( 2048,   20,    8),
106    //     ( 2048,   26,    8),
107    //     ( 2048,   44,    8),
108    //     ( 2048,   73,    8),
109    //     ( 2048,  256,    8)),
110    Seq(( 4096,    8,    8),
111        ( 4096,   13,    8),
112        ( 4096,   32,    8),
113        ( 4096,  119,    8)),
114  ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] =
115  //      Sets  Hist   Tag
116    Seq(( 256,    4,    9),
117        ( 256,    8,    9),
118        ( 512,   13,    9),
119        ( 512,   16,    9),
120        ( 512,   32,    9)),
121  SCNRows: Int = 512,
122  SCNTables: Int = 4,
123  SCCtrBits: Int = 6,
124  SCHistLens: Seq[Int] = Seq(0, 4, 10, 16),
125  numBr: Int = 2,
126  branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
127    ((resp_in: BranchPredictionResp, p: Parameters) => {
128      val ftb = Module(new FTB()(p))
129      val ubtb =Module(new FauFTB()(p))
130      // val bim = Module(new BIM()(p))
131      val tage = Module(new Tage_SC()(p))
132      val ras = Module(new RAS()(p))
133      val ittage = Module(new ITTage()(p))
134      val preds = Seq(ubtb, tage, ftb, ittage, ras)
135      preds.map(_.io := DontCare)
136
137      // ubtb.io.resp_in(0)  := resp_in
138      // bim.io.resp_in(0)   := ubtb.io.resp
139      // btb.io.resp_in(0)   := bim.io.resp
140      // tage.io.resp_in(0)  := btb.io.resp
141      // loop.io.resp_in(0)  := tage.io.resp
142      ubtb.io.in.bits.resp_in(0) := resp_in
143      tage.io.in.bits.resp_in(0) := ubtb.io.out
144      ftb.io.in.bits.resp_in(0)  := tage.io.out
145      ittage.io.in.bits.resp_in(0)  := ftb.io.out
146      ras.io.in.bits.resp_in(0) := ittage.io.out
147
148      (preds, ras.io.out)
149    }),
150  ICacheECCForceError: Boolean = false,
151  IBufSize: Int = 48,
152  IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize
153  DecodeWidth: Int = 6,
154  RenameWidth: Int = 6,
155  CommitWidth: Int = 6,
156  MaxUopSize: Int = 65,
157  EnableRenameSnapshot: Boolean = true,
158  RenameSnapshotNum: Int = 4,
159  FtqSize: Int = 64,
160  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
161  IntLogicRegs: Int = 32,
162  FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride
163  VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig
164  VCONFIG_IDX: Int = 32,
165  NRPhyRegs: Int = 192,
166  VirtualLoadQueueSize: Int = 72,
167  LoadQueueRARSize: Int = 72,
168  LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2.
169  RollbackGroupSize: Int = 8,
170  LoadQueueReplaySize: Int = 72,
171  LoadUncacheBufferSize: Int = 20,
172  LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks
173  StoreQueueSize: Int = 64,
174  StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
175  StoreQueueForwardWithMask: Boolean = true,
176  VlsQueueSize: Int = 8,
177  RobSize: Int = 160,
178  RabSize: Int = 256,
179  VTypeBufferSize: Int = 64, // used to reorder vtype
180  IssueQueueSize: Int = 24,
181  IssueQueueCompEntrySize: Int = 16,
182  dpParams: DispatchParameters = DispatchParameters(
183    IntDqSize = 16,
184    FpDqSize = 16,
185    LsDqSize = 18,
186    IntDqDeqWidth = 8,
187    FpDqDeqWidth = 6,
188    LsDqDeqWidth = 6,
189  ),
190  intPreg: PregParams = IntPregParams(
191    numEntries = 224,
192    numRead = None,
193    numWrite = None,
194  ),
195  vfPreg: VfPregParams = VfPregParams(
196    numEntries = 192,
197    numRead = Some(14),
198    numWrite = None,
199  ),
200  prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
201  LoadPipelineWidth: Int = 3,
202  StorePipelineWidth: Int = 2,
203  VecLoadPipelineWidth: Int = 2,
204  VecStorePipelineWidth: Int = 2,
205  VecMemSrcInWidth: Int = 2,
206  VecMemInstWbWidth: Int = 1,
207  VecMemDispatchWidth: Int = 1,
208  StoreBufferSize: Int = 16,
209  StoreBufferThreshold: Int = 7,
210  EnsbufferWidth: Int = 2,
211  // ============ VLSU ============
212  UsQueueSize: Int = 8,
213  VlFlowSize: Int = 32,
214  VlUopSize: Int = 32,
215  VsFlowL1Size: Int = 128,
216  VsFlowL2Size: Int = 32,
217  VsUopSize: Int = 32,
218  // ==============================
219  UncacheBufferSize: Int = 4,
220  EnableLoadToLoadForward: Boolean = false,
221  EnableFastForward: Boolean = true,
222  EnableLdVioCheckAfterReset: Boolean = true,
223  EnableSoftPrefetchAfterReset: Boolean = true,
224  EnableCacheErrorAfterReset: Boolean = true,
225  EnableAccurateLoadError: Boolean = true,
226  EnableUncacheWriteOutstanding: Boolean = false,
227  EnableStorePrefetchAtIssue: Boolean = false,
228  EnableStorePrefetchAtCommit: Boolean = false,
229  EnableAtCommitMissTrigger: Boolean = true,
230  EnableStorePrefetchSMS: Boolean = false,
231  EnableStorePrefetchSPB: Boolean = false,
232  MMUAsidLen: Int = 16, // max is 16, 0 is not supported now
233  MMUVmidLen: Int = 14,
234  ReSelectLen: Int = 7, // load replay queue replay select counter len
235  iwpuParameters: WPUParameters = WPUParameters(
236    enWPU = false,
237    algoName = "mmru",
238    isICache = true,
239  ),
240  dwpuParameters: WPUParameters = WPUParameters(
241    enWPU = false,
242    algoName = "mmru",
243    enCfPred = false,
244    isICache = false,
245  ),
246  itlbParameters: TLBParameters = TLBParameters(
247    name = "itlb",
248    fetchi = true,
249    useDmode = false,
250    NWays = 48,
251  ),
252  itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1,
253  ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1,
254  ldtlbParameters: TLBParameters = TLBParameters(
255    name = "ldtlb",
256    NWays = 48,
257    outReplace = false,
258    partialStaticPMP = true,
259    outsideRecvFlush = true,
260    saveLevel = true
261  ),
262  sttlbParameters: TLBParameters = TLBParameters(
263    name = "sttlb",
264    NWays = 48,
265    outReplace = false,
266    partialStaticPMP = true,
267    outsideRecvFlush = true,
268    saveLevel = true
269  ),
270  hytlbParameters: TLBParameters = TLBParameters(
271    name = "hytlb",
272    NWays = 48,
273    outReplace = false,
274    partialStaticPMP = true,
275    outsideRecvFlush = true,
276    saveLevel = true
277  ),
278  pftlbParameters: TLBParameters = TLBParameters(
279    name = "pftlb",
280    NWays = 48,
281    outReplace = false,
282    partialStaticPMP = true,
283    outsideRecvFlush = true,
284    saveLevel = true
285  ),
286  refillBothTlb: Boolean = false,
287  btlbParameters: TLBParameters = TLBParameters(
288    name = "btlb",
289    NWays = 48,
290  ),
291  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
292  NumPerfCounters: Int = 16,
293  icacheParameters: ICacheParameters = ICacheParameters(
294    tagECC = Some("parity"),
295    dataECC = Some("parity"),
296    replacer = Some("setplru"),
297    nMissEntries = 2,
298    nProbeEntries = 2,
299    nPrefetchEntries = 12,
300    nPrefBufferEntries = 32,
301  ),
302  dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
303    tagECC = Some("secded"),
304    dataECC = Some("secded"),
305    replacer = Some("setplru"),
306    nMissEntries = 16,
307    nProbeEntries = 8,
308    nReleaseEntries = 18,
309    nMaxPrefetchEntry = 6,
310  )),
311  L2CacheParamsOpt: Option[L2Param] = Some(L2Param(
312    name = "l2",
313    ways = 8,
314    sets = 1024, // default 512KB L2
315    prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams())
316  )),
317  L2NBanks: Int = 1,
318  usePTWRepeater: Boolean = false,
319  softTLB: Boolean = false, // dpi-c l1tlb debug only
320  softPTW: Boolean = false, // dpi-c l2tlb debug only
321  softPTWDelay: Int = 1
322){
323  def vlWidth = log2Up(VLEN) + 1
324
325  val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
326  val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
327
328  val intSchdParams = {
329    implicit val schdType: SchedulerType = IntScheduler()
330    SchdBlockParams(Seq(
331      IssueBlockParams(Seq(
332        ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2),
333        ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2),
334      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
335      IssueBlockParams(Seq(
336        ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2),
337        ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2),
338      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
339      IssueBlockParams(Seq(
340        ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2),
341        ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))),
342      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
343      IssueBlockParams(Seq(
344        ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2),
345        ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))),
346      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
347    ),
348      numPregs = intPreg.numEntries,
349      numDeqOutside = 0,
350      schdType = schdType,
351      rfDataWidth = intPreg.dataCfg.dataWidth,
352      numUopIn = dpParams.IntDqDeqWidth,
353    )
354  }
355  val vfSchdParams = {
356    implicit val schdType: SchedulerType = VfScheduler()
357    SchdBlockParams(Seq(
358      IssueBlockParams(Seq(
359        ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VimacCfg), Seq(VfWB(port = 5, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))),
360        ExeUnitParams("VFEX1", Seq(VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 6, 1), IntWB(port = 1, 2)), Seq(Seq(VfRD(5, 1)), Seq(VfRD(6, 1)), Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)))),
361      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
362      IssueBlockParams(Seq(
363        ExeUnitParams("VFEX2", Seq(VfaluCfg, VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))),
364        ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(VfRD(3, 1)), Seq(VfRD(4, 1)))),
365      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
366    ),
367      numPregs = vfPreg.numEntries,
368      numDeqOutside = 0,
369      schdType = schdType,
370      rfDataWidth = vfPreg.dataCfg.dataWidth,
371      numUopIn = dpParams.FpDqDeqWidth,
372    )
373  }
374
375  val memSchdParams = {
376    implicit val schdType: SchedulerType = MemScheduler()
377    val rfDataWidth = 64
378
379    SchdBlockParams(Seq(
380      IssueBlockParams(Seq(
381        ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))),
382      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
383      IssueBlockParams(Seq(
384        ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))),
385      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
386      IssueBlockParams(Seq(
387        ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2),
388      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
389      IssueBlockParams(Seq(
390        ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2),
391      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
392      IssueBlockParams(Seq(
393        ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2),
394      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
395      IssueBlockParams(Seq(
396        ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))),
397      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
398      IssueBlockParams(Seq(
399        ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))),
400      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
401      IssueBlockParams(Seq(
402        ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))),
403      ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
404    ),
405      numPregs = intPreg.numEntries max vfPreg.numEntries,
406      numDeqOutside = 0,
407      schdType = schdType,
408      rfDataWidth = rfDataWidth,
409      numUopIn = dpParams.LsDqDeqWidth,
410    )
411  }
412
413  def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth
414
415  def iqWakeUpParams = {
416    Seq(
417      WakeUpConfig(
418        Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") ->
419        Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1")
420      ),
421    ).flatten
422  }
423
424  def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite)
425
426  val backendParams: BackendParams = backend.BackendParams(
427    Map(
428      IntScheduler() -> intSchdParams,
429      VfScheduler() -> vfSchdParams,
430      MemScheduler() -> memSchdParams,
431    ),
432    Seq(
433      intPreg,
434      vfPreg,
435      fakeIntPreg
436    ),
437    iqWakeUpParams,
438  )
439}
440
441case object DebugOptionsKey extends Field[DebugOptions]
442
443case class DebugOptions
444(
445  FPGAPlatform: Boolean = false,
446  EnableDifftest: Boolean = false,
447  AlwaysBasicDiff: Boolean = true,
448  EnableDebug: Boolean = false,
449  EnablePerfDebug: Boolean = true,
450  UseDRAMSim: Boolean = false,
451  EnableConstantin: Boolean = false,
452  EnableChiselDB: Boolean = false,
453  AlwaysBasicDB: Boolean = true,
454  EnableTopDown: Boolean = false,
455  EnableRollingDB: Boolean = false
456)
457
458trait HasXSParameter {
459
460  implicit val p: Parameters
461
462  val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits
463
464  val coreParams = p(XSCoreParamsKey)
465  val env = p(DebugOptionsKey)
466
467  val XLEN = coreParams.XLEN
468  val VLEN = coreParams.VLEN
469  val ELEN = coreParams.ELEN
470  val HSXLEN = coreParams.HSXLEN
471  val minFLen = 32
472  val fLen = 64
473  val hartIdLen = p(MaxHartIdBits)
474  def xLen = XLEN
475
476  val HasMExtension = coreParams.HasMExtension
477  val HasCExtension = coreParams.HasCExtension
478  val HasHExtension = coreParams.HasHExtension
479  val HasDiv = coreParams.HasDiv
480  val HasIcache = coreParams.HasICache
481  val HasDcache = coreParams.HasDCache
482  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
483  val GPAddrBits = coreParams.GPAddrBits
484  val VAddrBits = {
485    if(HasHExtension){
486      coreParams.GPAddrBits
487    }else{
488      coreParams.VAddrBits
489    }
490  } // VAddrBits is Virtual Memory addr bits
491
492  val AsidLength = coreParams.AsidLength
493  val VmidLength = coreParams.VmidLength
494  val ReSelectLen = coreParams.ReSelectLen
495  val AddrBytes = AddrBits / 8 // unused
496  val DataBits = XLEN
497  val DataBytes = DataBits / 8
498  val VDataBytes = VLEN / 8
499  val HasFPU = coreParams.HasFPU
500  val HasVPU = coreParams.HasVPU
501  val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp
502  val FetchWidth = coreParams.FetchWidth
503  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
504  val EnableBPU = coreParams.EnableBPU
505  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
506  val EnableRAS = coreParams.EnableRAS
507  val EnableLB = coreParams.EnableLB
508  val EnableLoop = coreParams.EnableLoop
509  val EnableSC = coreParams.EnableSC
510  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
511  val HistoryLength = coreParams.HistoryLength
512  val EnableGHistDiff = coreParams.EnableGHistDiff
513  val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff
514  val EnableClockGate = coreParams.EnableClockGate
515  val UbtbGHRLength = coreParams.UbtbGHRLength
516  val UbtbSize = coreParams.UbtbSize
517  val EnableFauFTB = coreParams.EnableFauFTB
518  val FtbSize = coreParams.FtbSize
519  val FtbWays = coreParams.FtbWays
520  val RasSize = coreParams.RasSize
521  val RasSpecSize = coreParams.RasSpecSize
522  val RasCtrSize = coreParams.RasCtrSize
523
524  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = {
525    coreParams.branchPredictor(resp_in, p)
526  }
527  val numBr = coreParams.numBr
528  val TageTableInfos = coreParams.TageTableInfos
529  val TageBanks = coreParams.numBr
530  val SCNRows = coreParams.SCNRows
531  val SCCtrBits = coreParams.SCCtrBits
532  val SCHistLens = coreParams.SCHistLens
533  val SCNTables = coreParams.SCNTables
534
535  val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map {
536    case ((n, cb), h) => (n, cb, h)
537  }
538  val ITTageTableInfos = coreParams.ITTageTableInfos
539  type FoldedHistoryInfo = Tuple2[Int, Int]
540  val foldedGHistInfos =
541    (TageTableInfos.map{ case (nRows, h, t) =>
542      if (h > 0)
543        Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1)))
544      else
545        Set[FoldedHistoryInfo]()
546    }.reduce(_++_).toSet ++
547    SCTableInfos.map{ case (nRows, _, h) =>
548      if (h > 0)
549        Set((h, min(log2Ceil(nRows/TageBanks), h)))
550      else
551        Set[FoldedHistoryInfo]()
552    }.reduce(_++_).toSet ++
553    ITTageTableInfos.map{ case (nRows, h, t) =>
554      if (h > 0)
555        Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1)))
556      else
557        Set[FoldedHistoryInfo]()
558    }.reduce(_++_) ++
559      Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize)))
560    ).toList
561
562
563
564  val CacheLineSize = coreParams.CacheLineSize
565  val CacheLineHalfWord = CacheLineSize / 16
566  val ExtHistoryLength = HistoryLength + 64
567  val ICacheECCForceError = coreParams.ICacheECCForceError
568  val IBufSize = coreParams.IBufSize
569  val IBufNBank = coreParams.IBufNBank
570  val backendParams: BackendParams = coreParams.backendParams
571  val DecodeWidth = coreParams.DecodeWidth
572  val RenameWidth = coreParams.RenameWidth
573  val CommitWidth = coreParams.CommitWidth
574  val MaxUopSize = coreParams.MaxUopSize
575  val EnableRenameSnapshot = coreParams.EnableRenameSnapshot
576  val RenameSnapshotNum = coreParams.RenameSnapshotNum
577  val FtqSize = coreParams.FtqSize
578  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
579  val IntLogicRegs = coreParams.IntLogicRegs
580  val FpLogicRegs = coreParams.FpLogicRegs
581  val VecLogicRegs = coreParams.VecLogicRegs
582  val VCONFIG_IDX = coreParams.VCONFIG_IDX
583  val IntPhyRegs = coreParams.intPreg.numEntries
584  val VfPhyRegs = coreParams.vfPreg.numEntries
585  val MaxPhyPregs = IntPhyRegs max VfPhyRegs
586  val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs)
587  val RobSize = coreParams.RobSize
588  val RabSize = coreParams.RabSize
589  val VTypeBufferSize = coreParams.VTypeBufferSize
590  val IntRefCounterWidth = log2Ceil(RobSize)
591  val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth
592  val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp
593  val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp
594  val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize
595  val LoadQueueRARSize = coreParams.LoadQueueRARSize
596  val LoadQueueRAWSize = coreParams.LoadQueueRAWSize
597  val RollbackGroupSize = coreParams.RollbackGroupSize
598  val LoadQueueReplaySize = coreParams.LoadQueueReplaySize
599  val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize
600  val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks
601  val StoreQueueSize = coreParams.StoreQueueSize
602  val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks
603  val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask
604  val VlsQueueSize = coreParams.VlsQueueSize
605  val dpParams = coreParams.dpParams
606
607  def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max
608  def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max
609
610  val NumRedirect = backendParams.numRedirect
611  val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception
612  val FtqRedirectAheadNum = NumRedirect
613  val LoadPipelineWidth = coreParams.LoadPipelineWidth
614  val StorePipelineWidth = coreParams.StorePipelineWidth
615  val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth
616  val VecStorePipelineWidth = coreParams.VecStorePipelineWidth
617  val VecMemSrcInWidth = coreParams.VecMemSrcInWidth
618  val VecMemInstWbWidth = coreParams.VecMemInstWbWidth
619  val VecMemDispatchWidth = coreParams.VecMemDispatchWidth
620  val StoreBufferSize = coreParams.StoreBufferSize
621  val StoreBufferThreshold = coreParams.StoreBufferThreshold
622  val EnsbufferWidth = coreParams.EnsbufferWidth
623  val UsQueueSize = coreParams.UsQueueSize
624  val VlFlowSize = coreParams.VlFlowSize
625  val VlUopSize = coreParams.VlUopSize
626  val VsFlowL1Size = coreParams.VsFlowL1Size
627  val VsFlowL2Size = coreParams.VsFlowL2Size
628  val VsUopSize = coreParams.VsUopSize
629  val UncacheBufferSize = coreParams.UncacheBufferSize
630  val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward
631  val EnableFastForward = coreParams.EnableFastForward
632  val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset
633  val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset
634  val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset
635  val EnableAccurateLoadError = coreParams.EnableAccurateLoadError
636  val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding
637  val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue
638  val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit
639  val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger
640  val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS
641  val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB
642  require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!")
643  require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!")
644  val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3)
645  val asidLen = coreParams.MMUAsidLen
646  val vmidLen = coreParams.MMUVmidLen
647  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
648  val refillBothTlb = coreParams.refillBothTlb
649  val iwpuParam = coreParams.iwpuParameters
650  val dwpuParam = coreParams.dwpuParameters
651  val itlbParams = coreParams.itlbParameters
652  val ldtlbParams = coreParams.ldtlbParameters
653  val sttlbParams = coreParams.sttlbParameters
654  val hytlbParams = coreParams.hytlbParameters
655  val pftlbParams = coreParams.pftlbParameters
656  val btlbParams = coreParams.btlbParameters
657  val l2tlbParams = coreParams.l2tlbParameters
658  val NumPerfCounters = coreParams.NumPerfCounters
659
660  val instBytes = if (HasCExtension) 2 else 4
661  val instOffsetBits = log2Ceil(instBytes)
662
663  val icacheParameters = coreParams.icacheParameters
664  val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
665
666  // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles
667  // for constrained LR/SC loop
668  val LRSCCycles = 64
669  // for lr storm
670  val LRSCBackOff = 8
671
672  // cache hierarchy configurations
673  val l1BusDataWidth = 256
674
675  // load violation predict
676  val ResetTimeMax2Pow = 20 //1078576
677  val ResetTimeMin2Pow = 10 //1024
678  // wait table parameters
679  val WaitTableSize = 1024
680  val MemPredPCWidth = log2Up(WaitTableSize)
681  val LWTUse2BitCounter = true
682  // store set parameters
683  val SSITSize = WaitTableSize
684  val LFSTSize = 32
685  val SSIDWidth = log2Up(LFSTSize)
686  val LFSTWidth = 4
687  val StoreSetEnable = true // LWT will be disabled if SS is enabled
688  val LFSTEnable = true
689
690  val PCntIncrStep: Int = 6
691  val numPCntHc: Int = 25
692  val numPCntPtw: Int = 19
693
694  val numCSRPCntFrontend = 8
695  val numCSRPCntCtrl     = 8
696  val numCSRPCntLsu      = 8
697  val numCSRPCntHc       = 5
698  val printEventCoding   = true
699
700  // Parameters for Sdtrig extension
701  protected val TriggerNum = 4
702  protected val TriggerChainMaxLength = 2
703}
704