1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.frontend.icache.ICacheParameters 29import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 30import freechips.rocketchip.diplomacy.AddressSet 31import system.SoCParamsKey 32import scala.math.min 33 34case object XSTileKey extends Field[Seq[XSCoreParameters]] 35 36case object XSCoreParamsKey extends Field[XSCoreParameters] 37 38case class XSCoreParameters 39( 40 HasPrefetch: Boolean = false, 41 HartId: Int = 0, 42 XLEN: Int = 64, 43 HasMExtension: Boolean = true, 44 HasCExtension: Boolean = true, 45 HasDiv: Boolean = true, 46 HasICache: Boolean = true, 47 HasDCache: Boolean = true, 48 AddrBits: Int = 64, 49 VAddrBits: Int = 39, 50 HasFPU: Boolean = true, 51 HasCustomCSRCacheOp: Boolean = true, 52 FetchWidth: Int = 8, 53 AsidLength: Int = 16, 54 EnableBPU: Boolean = true, 55 EnableBPD: Boolean = true, 56 EnableRAS: Boolean = true, 57 EnableLB: Boolean = false, 58 EnableLoop: Boolean = true, 59 EnableSC: Boolean = true, 60 EnbaleTlbDebug: Boolean = false, 61 EnableJal: Boolean = false, 62 EnableUBTB: Boolean = true, 63 HistoryLength: Int = 256, 64 PathHistoryLength: Int = 16, 65 BtbSize: Int = 2048, 66 JbtacSize: Int = 1024, 67 JbtacBanks: Int = 8, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 UBtbWays: Int = 16, 71 BtbWays: Int = 2, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 Seq(( 128*8, 2, 7), 75 ( 128*8, 4, 7), 76 ( 256*8, 8, 8), 77 ( 256*8, 16, 8), 78 ( 128*8, 32, 9), 79 ( 128*8, 65, 9)), 80 TageBanks: Int = 2, 81 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 82 // Sets Hist Tag 83 Seq(( 512, 0, 0), 84 ( 256, 4, 8), 85 ( 256, 8, 8), 86 ( 512, 12, 8), 87 ( 512, 16, 8), 88 ( 512, 32, 8)), 89 SCNRows: Int = 1024, 90 SCNTables: Int = 6, 91 SCCtrBits: Int = 6, 92 numBr: Int = 2, 93 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 94 ((resp_in: BranchPredictionResp, p: Parameters) => { 95 // val loop = Module(new LoopPredictor) 96 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 97 // else Module(new Tage) } 98 // else { Module(new FakeTage) }) 99 val ftb = Module(new FTB()(p)) 100 val ubtb = Module(new MicroBTB()(p)) 101 val bim = Module(new BIM()(p)) 102 val tage = Module(new Tage_SC()(p)) 103 val ras = Module(new RAS()(p)) 104 val ittage = Module(new ITTage()(p)) 105 // val tage = Module(new Tage()(p)) 106 // val fake = Module(new FakePredictor()(p)) 107 108 // val preds = Seq(loop, tage, btb, ubtb, bim) 109 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 110 preds.map(_.io := DontCare) 111 112 // ubtb.io.resp_in(0) := resp_in 113 // bim.io.resp_in(0) := ubtb.io.resp 114 // btb.io.resp_in(0) := bim.io.resp 115 // tage.io.resp_in(0) := btb.io.resp 116 // loop.io.resp_in(0) := tage.io.resp 117 bim.io.in.bits.resp_in(0) := resp_in 118 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 119 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 120 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 121 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 122 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 123 124 (preds, ras.io.out.resp) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 FtqSize: Int = 64, 131 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 132 IssQueSize: Int = 16, 133 NRPhyRegs: Int = 192, 134 NRIntReadPorts: Int = 14, 135 NRIntWritePorts: Int = 8, 136 NRFpReadPorts: Int = 14, 137 NRFpWritePorts: Int = 8, 138 LoadQueueSize: Int = 80, 139 StoreQueueSize: Int = 64, 140 RobSize: Int = 256, 141 dpParams: DispatchParameters = DispatchParameters( 142 IntDqSize = 16, 143 FpDqSize = 16, 144 LsDqSize = 16, 145 IntDqDeqWidth = 4, 146 FpDqDeqWidth = 4, 147 LsDqDeqWidth = 4 148 ), 149 exuParameters: ExuParameters = ExuParameters( 150 JmpCnt = 1, 151 AluCnt = 4, 152 MulCnt = 0, 153 MduCnt = 2, 154 FmacCnt = 4, 155 FmiscCnt = 2, 156 FmiscDivSqrtCnt = 0, 157 LduCnt = 2, 158 StuCnt = 2 159 ), 160 LoadPipelineWidth: Int = 2, 161 StorePipelineWidth: Int = 2, 162 StoreBufferSize: Int = 16, 163 StoreBufferThreshold: Int = 7, 164 EnableFastForward: Boolean = false, 165 EnableLdVioCheckAfterReset: Boolean = true, 166 RefillSize: Int = 512, 167 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 168 itlbParameters: TLBParameters = TLBParameters( 169 name = "itlb", 170 fetchi = true, 171 useDmode = false, 172 sameCycle = true, 173 normalNWays = 32, 174 normalReplacer = Some("plru"), 175 superNWays = 4, 176 superReplacer = Some("plru"), 177 shouldBlock = true 178 ), 179 ldtlbParameters: TLBParameters = TLBParameters( 180 name = "ldtlb", 181 normalNSets = 128, 182 normalNWays = 1, 183 normalAssociative = "sa", 184 normalReplacer = Some("setplru"), 185 superNWays = 8, 186 normalAsVictim = true, 187 outReplace = true, 188 saveLevel = true 189 ), 190 sttlbParameters: TLBParameters = TLBParameters( 191 name = "sttlb", 192 normalNSets = 128, 193 normalNWays = 1, 194 normalAssociative = "sa", 195 normalReplacer = Some("setplru"), 196 superNWays = 8, 197 normalAsVictim = true, 198 outReplace = true, 199 saveLevel = true 200 ), 201 refillBothTlb: Boolean = false, 202 btlbParameters: TLBParameters = TLBParameters( 203 name = "btlb", 204 normalNSets = 1, 205 normalNWays = 64, 206 superNWays = 4, 207 ), 208 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 209 NumPMP: Int = 16, // 0 or 16 or 64 210 NumPMA: Int = 16, 211 NumPerfCounters: Int = 16, 212 icacheParameters: ICacheParameters = ICacheParameters( 213 tagECC = Some("secded"), 214 dataECC = Some("parity"), 215 replacer = Some("setplru"), 216 nMissEntries = 2, 217 nReleaseEntries = 2 218 ), 219 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 220 tagECC = Some("secded"), 221 dataECC = Some("secded"), 222 replacer = Some("setplru"), 223 nMissEntries = 16, 224 nProbeEntries = 8, 225 nReleaseEntries = 18 226 )), 227 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 228 name = "l2", 229 level = 2, 230 ways = 8, 231 sets = 1024, // default 512KB L2 232 prefetch = Some(huancun.prefetch.BOPParameters()) 233 )), 234 L2NBanks: Int = 1, 235 usePTWRepeater: Boolean = false, 236 softPTW: Boolean = false // dpi-c debug only 237){ 238 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 239 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 240 241 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 242 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 243 244 val fpExuConfigs = 245 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 246 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 247 248 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 249} 250 251case object DebugOptionsKey extends Field[DebugOptions] 252 253case class DebugOptions 254( 255 FPGAPlatform: Boolean = false, 256 EnableDifftest: Boolean = false, 257 AlwaysBasicDiff: Boolean = true, 258 EnableDebug: Boolean = false, 259 EnablePerfDebug: Boolean = true, 260 UseDRAMSim: Boolean = false 261) 262 263trait HasXSParameter { 264 265 implicit val p: Parameters 266 267 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 268 269 val coreParams = p(XSCoreParamsKey) 270 val env = p(DebugOptionsKey) 271 272 val XLEN = coreParams.XLEN 273 val minFLen = 32 274 val fLen = 64 275 def xLen = XLEN 276 277 val HasMExtension = coreParams.HasMExtension 278 val HasCExtension = coreParams.HasCExtension 279 val HasDiv = coreParams.HasDiv 280 val HasIcache = coreParams.HasICache 281 val HasDcache = coreParams.HasDCache 282 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 283 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 284 val AsidLength = coreParams.AsidLength 285 val AddrBytes = AddrBits / 8 // unused 286 val DataBits = XLEN 287 val DataBytes = DataBits / 8 288 val HasFPU = coreParams.HasFPU 289 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 290 val FetchWidth = coreParams.FetchWidth 291 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 292 val EnableBPU = coreParams.EnableBPU 293 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 294 val EnableRAS = coreParams.EnableRAS 295 val EnableLB = coreParams.EnableLB 296 val EnableLoop = coreParams.EnableLoop 297 val EnableSC = coreParams.EnableSC 298 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 299 val HistoryLength = coreParams.HistoryLength 300 val PathHistoryLength = coreParams.PathHistoryLength 301 val BtbSize = coreParams.BtbSize 302 // val BtbWays = 4 303 val BtbBanks = PredictWidth 304 // val BtbSets = BtbSize / BtbWays 305 val JbtacSize = coreParams.JbtacSize 306 val JbtacBanks = coreParams.JbtacBanks 307 val RasSize = coreParams.RasSize 308 309 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 310 coreParams.branchPredictor(resp_in, p) 311 } 312 val numBr = coreParams.numBr 313 val TageTableInfos = coreParams.TageTableInfos 314 315 316 val BankTageTableInfos = (0 until numBr).map(i => 317 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 318 ) 319 val TageBanks = coreParams.TageBanks 320 val SCNRows = coreParams.SCNRows 321 val SCCtrBits = coreParams.SCCtrBits 322 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 323 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 324 325 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 326 case (ntable, histlens) => 327 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 328 } 329 val ITTageTableInfos = coreParams.ITTageTableInfos 330 type FoldedHistoryInfo = Tuple2[Int, Int] 331 val foldedGHistInfos = 332 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 333 if (h > 0) 334 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 335 else 336 Set[FoldedHistoryInfo]() 337 }.reduce(_++_)).toSet ++ 338 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 339 if (h > 0) 340 Set((h, min(log2Ceil(nRows/TageBanks), h))) 341 else 342 Set[FoldedHistoryInfo]() 343 }.reduce(_++_)).toSet ++ 344 ITTageTableInfos.map{ case (nRows, h, t) => 345 if (h > 0) 346 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 347 else 348 Set[FoldedHistoryInfo]() 349 }.reduce(_++_)).toList 350 351 val CacheLineSize = coreParams.CacheLineSize 352 val CacheLineHalfWord = CacheLineSize / 16 353 val ExtHistoryLength = HistoryLength + 64 354 val UBtbWays = coreParams.UBtbWays 355 val BtbWays = coreParams.BtbWays 356 val IBufSize = coreParams.IBufSize 357 val DecodeWidth = coreParams.DecodeWidth 358 val RenameWidth = coreParams.RenameWidth 359 val CommitWidth = coreParams.CommitWidth 360 val FtqSize = coreParams.FtqSize 361 val IssQueSize = coreParams.IssQueSize 362 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 363 val NRPhyRegs = coreParams.NRPhyRegs 364 val PhyRegIdxWidth = log2Up(NRPhyRegs) 365 val RobSize = coreParams.RobSize 366 val IntRefCounterWidth = log2Ceil(RobSize) 367 val LoadQueueSize = coreParams.LoadQueueSize 368 val StoreQueueSize = coreParams.StoreQueueSize 369 val dpParams = coreParams.dpParams 370 val exuParameters = coreParams.exuParameters 371 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 372 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 373 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 374 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 375 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 376 val LoadPipelineWidth = coreParams.LoadPipelineWidth 377 val StorePipelineWidth = coreParams.StorePipelineWidth 378 val StoreBufferSize = coreParams.StoreBufferSize 379 val StoreBufferThreshold = coreParams.StoreBufferThreshold 380 val EnableFastForward = coreParams.EnableFastForward 381 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 382 val RefillSize = coreParams.RefillSize 383 val asidLen = coreParams.MMUAsidLen 384 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 385 val refillBothTlb = coreParams.refillBothTlb 386 val itlbParams = coreParams.itlbParameters 387 val ldtlbParams = coreParams.ldtlbParameters 388 val sttlbParams = coreParams.sttlbParameters 389 val btlbParams = coreParams.btlbParameters 390 val l2tlbParams = coreParams.l2tlbParameters 391 val NumPMP = coreParams.NumPMP 392 val NumPMA = coreParams.NumPMA 393 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 394 val NumPerfCounters = coreParams.NumPerfCounters 395 396 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 397 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 398 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 399 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 400 401 val instBytes = if (HasCExtension) 2 else 4 402 val instOffsetBits = log2Ceil(instBytes) 403 404 val icacheParameters = coreParams.icacheParameters 405 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 406 407 val LRSCCycles = 100 408 409 // cache hierarchy configurations 410 val l1BusDataWidth = 256 411 412 // load violation predict 413 val ResetTimeMax2Pow = 20 //1078576 414 val ResetTimeMin2Pow = 10 //1024 415 // wait table parameters 416 val WaitTableSize = 1024 417 val MemPredPCWidth = log2Up(WaitTableSize) 418 val LWTUse2BitCounter = true 419 // store set parameters 420 val SSITSize = WaitTableSize 421 val LFSTSize = 32 422 val SSIDWidth = log2Up(LFSTSize) 423 val LFSTWidth = 4 424 val StoreSetEnable = true // LWT will be disabled if SS is enabled 425 426 val loadExuConfigs = coreParams.loadExuConfigs 427 val storeExuConfigs = coreParams.storeExuConfigs 428 429 val intExuConfigs = coreParams.intExuConfigs 430 431 val fpExuConfigs = coreParams.fpExuConfigs 432 433 val exuConfigs = coreParams.exuConfigs 434 435 val PCntIncrStep: Int = 6 436 val numPCntHc: Int = 25 437 val numPCntPtw: Int = 19 438 439 val numCSRPCntFrontend = 8 440 val numCSRPCntCtrl = 8 441 val numCSRPCntLsu = 8 442 val numCSRPCntHc = 5 443 val print_perfcounter = false 444} 445