1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import system.CVMParamskey 25import xiangshan.backend.datapath.RdConfig._ 26import xiangshan.backend.datapath.WbConfig._ 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasBitmapCheck: Boolean = false, 65 HasBitmapCheckDefault: Boolean = false, 66 HasMExtension: Boolean = true, 67 HasCExtension: Boolean = true, 68 HasHExtension: Boolean = true, 69 HasDiv: Boolean = true, 70 HasICache: Boolean = true, 71 HasDCache: Boolean = true, 72 AddrBits: Int = 64, 73 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 74 VAddrBitsSv39: Int = 39, 75 GPAddrBitsSv39x4: Int = 41, 76 VAddrBitsSv48: Int = 48, 77 GPAddrBitsSv48x4: Int = 50, 78 HasFPU: Boolean = true, 79 HasVPU: Boolean = true, 80 HasCustomCSRCacheOp: Boolean = true, 81 FetchWidth: Int = 8, 82 AsidLength: Int = 16, 83 VmidLength: Int = 14, 84 EnableBPU: Boolean = true, 85 EnableBPD: Boolean = true, 86 EnableRAS: Boolean = true, 87 EnableLB: Boolean = false, 88 EnableLoop: Boolean = true, 89 EnableSC: Boolean = true, 90 EnbaleTlbDebug: Boolean = false, 91 EnableClockGate: Boolean = true, 92 EnableJal: Boolean = false, 93 EnableFauFTB: Boolean = true, 94 EnableSv48: Boolean = true, 95 UbtbGHRLength: Int = 4, 96 // HistoryLength: Int = 512, 97 EnableGHistDiff: Boolean = true, 98 EnableCommitGHistDiff: Boolean = true, 99 UbtbSize: Int = 256, 100 FtbSize: Int = 2048, 101 FtbWays: Int = 4, 102 FtbTagLength: Int = 20, 103 RasSize: Int = 16, 104 RasSpecSize: Int = 32, 105 RasCtrSize: Int = 3, 106 CacheLineSize: Int = 512, 107 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 108 // Sets Hist Tag 109 Seq(( 4096, 8, 8), 110 ( 4096, 13, 8), 111 ( 4096, 32, 8), 112 ( 4096, 119, 8)), 113 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 114 // Sets Hist Tag 115 Seq(( 256, 4, 9), 116 ( 256, 8, 9), 117 ( 512, 13, 9), 118 ( 512, 16, 9), 119 ( 512, 32, 9)), 120 SCNRows: Int = 512, 121 SCNTables: Int = 4, 122 SCCtrBits: Int = 6, 123 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 124 numBr: Int = 2, 125 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 126 (resp_in: BranchPredictionResp, p: Parameters) => { 127 val ftb = Module(new FTB()(p)) 128 val uftb = Module(new FauFTB()(p)) 129 val tage = Module(new Tage_SC()(p)) 130 val ras = Module(new RAS()(p)) 131 val ittage = Module(new ITTage()(p)) 132 val preds = Seq(uftb, tage, ftb, ittage, ras) 133 preds.map(_.io := DontCare) 134 135 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 136 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 137 138 uftb.io.in.bits.resp_in(0) := resp_in 139 tage.io.in.bits.resp_in(0) := uftb.io.out 140 ftb.io.in.bits.resp_in(0) := tage.io.out 141 ittage.io.in.bits.resp_in(0) := ftb.io.out 142 ras.io.in.bits.resp_in(0) := ittage.io.out 143 144 (preds, ras.io.out) 145 }, 146 ICacheForceMetaECCError: Boolean = false, 147 ICacheForceDataECCError: Boolean = false, 148 IBufSize: Int = 48, 149 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 150 DecodeWidth: Int = 6, 151 RenameWidth: Int = 6, 152 CommitWidth: Int = 8, 153 RobCommitWidth: Int = 8, 154 RabCommitWidth: Int = 6, 155 MaxUopSize: Int = 65, 156 EnableRenameSnapshot: Boolean = true, 157 RenameSnapshotNum: Int = 4, 158 FtqSize: Int = 64, 159 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 160 IntLogicRegs: Int = 32, 161 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 162 VecLogicRegs: Int = 32 + 15, // 15: tmp 163 V0LogicRegs: Int = 1, // V0 164 VlLogicRegs: Int = 1, // Vl 165 V0_IDX: Int = 0, 166 Vl_IDX: Int = 0, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 4, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 56, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 intPreg: PregParams = IntPregParams( 185 numEntries = 224, 186 numRead = None, 187 numWrite = None, 188 ), 189 fpPreg: PregParams = FpPregParams( 190 numEntries = 192, 191 numRead = None, 192 numWrite = None, 193 ), 194 vfPreg: VfPregParams = VfPregParams( 195 numEntries = 128, 196 numRead = None, 197 numWrite = None, 198 ), 199 v0Preg: V0PregParams = V0PregParams( 200 numEntries = 22, 201 numRead = None, 202 numWrite = None, 203 ), 204 vlPreg: VlPregParams = VlPregParams( 205 numEntries = 32, 206 numRead = None, 207 numWrite = None, 208 ), 209 IntRegCacheSize: Int = 16, 210 MemRegCacheSize: Int = 12, 211 intSchdVlWbPort: Int = 0, 212 vfSchdVlWbPort: Int = 1, 213 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 214 IfuRedirectNum: Int = 1, 215 LoadPipelineWidth: Int = 3, 216 StorePipelineWidth: Int = 2, 217 VecLoadPipelineWidth: Int = 2, 218 VecStorePipelineWidth: Int = 2, 219 VecMemSrcInWidth: Int = 2, 220 VecMemInstWbWidth: Int = 1, 221 VecMemDispatchWidth: Int = 1, 222 VecMemDispatchMaxNumber: Int = 16, 223 VecMemUnitStrideMaxFlowNum: Int = 2, 224 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16), 225 StoreBufferSize: Int = 16, 226 StoreBufferThreshold: Int = 7, 227 EnsbufferWidth: Int = 2, 228 LoadDependencyWidth: Int = 2, 229 // ============ VLSU ============ 230 VlMergeBufferSize: Int = 16, 231 VsMergeBufferSize: Int = 16, 232 UopWritebackWidth: Int = 2, 233 VLUopWritebackWidth: Int = 2, 234 VSUopWritebackWidth: Int = 1, 235 VSegmentBufferSize: Int = 8, 236 VFOFBufferSize: Int = 8, 237 VLFOFWritebackWidth: Int = 1, 238 // ============================== 239 UncacheBufferSize: Int = 4, 240 EnableLoadToLoadForward: Boolean = false, 241 EnableFastForward: Boolean = true, 242 EnableLdVioCheckAfterReset: Boolean = true, 243 EnableSoftPrefetchAfterReset: Boolean = true, 244 EnableCacheErrorAfterReset: Boolean = true, 245 EnableAccurateLoadError: Boolean = false, 246 EnableUncacheWriteOutstanding: Boolean = false, 247 EnableHardwareStoreMisalign: Boolean = true, 248 EnableHardwareLoadMisalign: Boolean = true, 249 EnableStorePrefetchAtIssue: Boolean = false, 250 EnableStorePrefetchAtCommit: Boolean = false, 251 EnableAtCommitMissTrigger: Boolean = true, 252 EnableStorePrefetchSMS: Boolean = false, 253 EnableStorePrefetchSPB: Boolean = false, 254 HasCMO: Boolean = true, 255 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 256 MMUVmidLen: Int = 14, 257 ReSelectLen: Int = 7, // load replay queue replay select counter len 258 iwpuParameters: WPUParameters = WPUParameters( 259 enWPU = false, 260 algoName = "mmru", 261 isICache = true, 262 ), 263 dwpuParameters: WPUParameters = WPUParameters( 264 enWPU = false, 265 algoName = "mmru", 266 enCfPred = false, 267 isICache = false, 268 ), 269 itlbParameters: TLBParameters = TLBParameters( 270 name = "itlb", 271 fetchi = true, 272 useDmode = false, 273 NWays = 48, 274 ), 275 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 276 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 277 ldtlbParameters: TLBParameters = TLBParameters( 278 name = "ldtlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = false, 284 lgMaxSize = 4 285 ), 286 sttlbParameters: TLBParameters = TLBParameters( 287 name = "sttlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = false, 293 lgMaxSize = 4 294 ), 295 hytlbParameters: TLBParameters = TLBParameters( 296 name = "hytlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = false, 302 lgMaxSize = 4 303 ), 304 pftlbParameters: TLBParameters = TLBParameters( 305 name = "pftlb", 306 NWays = 48, 307 outReplace = false, 308 partialStaticPMP = true, 309 outsideRecvFlush = true, 310 saveLevel = false, 311 lgMaxSize = 4 312 ), 313 l2ToL1tlbParameters: TLBParameters = TLBParameters( 314 name = "l2tlb", 315 NWays = 48, 316 outReplace = false, 317 partialStaticPMP = true, 318 outsideRecvFlush = true, 319 saveLevel = false 320 ), 321 refillBothTlb: Boolean = false, 322 btlbParameters: TLBParameters = TLBParameters( 323 name = "btlb", 324 NWays = 48, 325 ), 326 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 327 NumPerfCounters: Int = 16, 328 icacheParameters: ICacheParameters = ICacheParameters( 329 tagECC = Some("parity"), 330 dataECC = Some("parity"), 331 replacer = Some("setplru"), 332 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)) 333 ), 334 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 335 tagECC = Some("secded"), 336 dataECC = Some("secded"), 337 replacer = Some("setplru"), 338 nMissEntries = 16, 339 nProbeEntries = 8, 340 nReleaseEntries = 18, 341 nMaxPrefetchEntry = 6, 342 enableTagEcc = true, 343 enableDataEcc = true, 344 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 345 )), 346 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 347 name = "l2", 348 ways = 8, 349 sets = 1024, // default 512KB L2 350 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 351 coupledL2.prefetch.TPParameters()), 352 )), 353 L2NBanks: Int = 1, 354 usePTWRepeater: Boolean = false, 355 softTLB: Boolean = false, // dpi-c l1tlb debug only 356 softPTW: Boolean = false, // dpi-c l2tlb debug only 357 softPTWDelay: Int = 1 358){ 359 def ISABase = "rv64i" 360 def ISAExtensions = Seq( 361 // single letter extensions, in canonical order 362 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 363 // multi-letter extensions, sorted alphanumerically 364 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 365 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 366 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 367 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 368 "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", 369 "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", 370 "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", 371 "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", 372 "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 373 ) 374 375 def vlWidth = log2Up(VLEN) + 1 376 377 /** 378 * the minimum element length of vector elements 379 */ 380 val minVecElen: Int = 8 381 382 /** 383 * the maximum number of elements in vector register 384 */ 385 val maxElemPerVreg: Int = VLEN / minVecElen 386 387 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 388 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 389 390 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 391 val RegCacheIdxWidth = log2Up(RegCacheSize) 392 393 val intSchdParams = { 394 implicit val schdType: SchedulerType = IntScheduler() 395 SchdBlockParams(Seq( 396 IssueBlockParams(Seq( 397 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 398 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 399 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 400 IssueBlockParams(Seq( 401 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 402 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 403 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 404 IssueBlockParams(Seq( 405 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 406 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 407 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 408 IssueBlockParams(Seq( 409 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 410 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 411 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 412 ), 413 numPregs = intPreg.numEntries, 414 numDeqOutside = 0, 415 schdType = schdType, 416 rfDataWidth = intPreg.dataCfg.dataWidth, 417 ) 418 } 419 420 val fpSchdParams = { 421 implicit val schdType: SchedulerType = FpScheduler() 422 SchdBlockParams(Seq( 423 IssueBlockParams(Seq( 424 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 425 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 426 ), numEntries = 18, numEnq = 2, numComp = 14), 427 IssueBlockParams(Seq( 428 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 429 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 430 ), numEntries = 18, numEnq = 2, numComp = 14), 431 IssueBlockParams(Seq( 432 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 433 ), numEntries = 18, numEnq = 2, numComp = 14), 434 ), 435 numPregs = fpPreg.numEntries, 436 numDeqOutside = 0, 437 schdType = schdType, 438 rfDataWidth = fpPreg.dataCfg.dataWidth, 439 ) 440 } 441 442 val vfSchdParams = { 443 implicit val schdType: SchedulerType = VfScheduler() 444 SchdBlockParams(Seq( 445 IssueBlockParams(Seq( 446 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 447 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 448 ), numEntries = 16, numEnq = 2, numComp = 12), 449 IssueBlockParams(Seq( 450 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 451 ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 452 ), numEntries = 16, numEnq = 2, numComp = 12), 453 IssueBlockParams(Seq( 454 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 455 ), numEntries = 10, numEnq = 2, numComp = 6), 456 ), 457 numPregs = vfPreg.numEntries, 458 numDeqOutside = 0, 459 schdType = schdType, 460 rfDataWidth = vfPreg.dataCfg.dataWidth, 461 ) 462 } 463 464 val memSchdParams = { 465 implicit val schdType: SchedulerType = MemScheduler() 466 val rfDataWidth = 64 467 468 SchdBlockParams(Seq( 469 IssueBlockParams(Seq( 470 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 471 ), numEntries = 16, numEnq = 2, numComp = 12), 472 IssueBlockParams(Seq( 473 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 474 ), numEntries = 16, numEnq = 2, numComp = 12), 475 IssueBlockParams(Seq( 476 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 477 ), numEntries = 16, numEnq = 2, numComp = 12), 478 IssueBlockParams(Seq( 479 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 480 ), numEntries = 16, numEnq = 2, numComp = 12), 481 IssueBlockParams(Seq( 482 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 483 ), numEntries = 16, numEnq = 2, numComp = 12), 484 IssueBlockParams(Seq( 485 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 486 ), numEntries = 16, numEnq = 2, numComp = 12), 487 IssueBlockParams(Seq( 488 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 489 ), numEntries = 16, numEnq = 2, numComp = 12), 490 IssueBlockParams(Seq( 491 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 492 ), numEntries = 16, numEnq = 2, numComp = 12), 493 IssueBlockParams(Seq( 494 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 495 ), numEntries = 16, numEnq = 2, numComp = 12), 496 ), 497 numPregs = intPreg.numEntries max vfPreg.numEntries, 498 numDeqOutside = 0, 499 schdType = schdType, 500 rfDataWidth = rfDataWidth, 501 ) 502 } 503 504 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 505 506 def iqWakeUpParams = { 507 Seq( 508 WakeUpConfig( 509 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 510 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 511 ), 512 // TODO: add load -> fp slow wakeup 513 WakeUpConfig( 514 Seq("FEX0", "FEX2", "FEX4") -> 515 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 516 ), 517 ).flatten 518 } 519 520 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 521 522 val backendParams: BackendParams = backend.BackendParams( 523 Map( 524 IntScheduler() -> intSchdParams, 525 FpScheduler() -> fpSchdParams, 526 VfScheduler() -> vfSchdParams, 527 MemScheduler() -> memSchdParams, 528 ), 529 Seq( 530 intPreg, 531 fpPreg, 532 vfPreg, 533 v0Preg, 534 vlPreg, 535 fakeIntPreg 536 ), 537 iqWakeUpParams, 538 ) 539 540 // Parameters for trace extension. 541 // Trace parameters is useful for XSTOP. 542 val traceParams: TraceParams = new TraceParams( 543 TraceGroupNum = 3, 544 IaddrWidth = GPAddrBitsSv48x4, 545 PrivWidth = 3, 546 ItypeWidth = 4, 547 IlastsizeWidth = 1, 548 ) 549} 550 551case object DebugOptionsKey extends Field[DebugOptions] 552 553case class DebugOptions 554( 555 FPGAPlatform: Boolean = false, 556 ResetGen: Boolean = false, 557 EnableDifftest: Boolean = false, 558 AlwaysBasicDiff: Boolean = true, 559 EnableDebug: Boolean = false, 560 EnablePerfDebug: Boolean = true, 561 PerfLevel: String = "VERBOSE", 562 UseDRAMSim: Boolean = false, 563 EnableConstantin: Boolean = false, 564 EnableChiselDB: Boolean = false, 565 AlwaysBasicDB: Boolean = true, 566 EnableRollingDB: Boolean = false 567) 568 569trait HasXSParameter { 570 571 implicit val p: Parameters 572 573 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 574 def PmemRanges = p(SoCParamsKey).PmemRanges 575 def KeyIDBits = p(CVMParamskey).KeyIDBits 576 final val PageOffsetWidth = 12 577 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 578 579 def coreParams = p(XSCoreParamsKey) 580 def env = p(DebugOptionsKey) 581 582 def ISABase = coreParams.ISABase 583 def ISAExtensions = coreParams.ISAExtensions 584 def XLEN = coreParams.XLEN 585 def VLEN = coreParams.VLEN 586 def ELEN = coreParams.ELEN 587 def HSXLEN = coreParams.HSXLEN 588 val minFLen = 32 589 val fLen = 64 590 def hartIdLen = p(MaxHartIdBits) 591 val xLen = XLEN 592 593 def HasBitmapCheck = coreParams.HasBitmapCheck 594 def HasBitmapCheckDefault = coreParams.HasBitmapCheckDefault 595 def HasMExtension = coreParams.HasMExtension 596 def HasCExtension = coreParams.HasCExtension 597 def HasHExtension = coreParams.HasHExtension 598 def EnableSv48 = coreParams.EnableSv48 599 def HasDiv = coreParams.HasDiv 600 def HasIcache = coreParams.HasICache 601 def HasDcache = coreParams.HasDCache 602 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 603 def PAddrBitsMax = coreParams.PAddrBitsMax 604 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 605 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 606 def GPAddrBits = { 607 if (EnableSv48) 608 coreParams.GPAddrBitsSv48x4 609 else 610 coreParams.GPAddrBitsSv39x4 611 } 612 def VAddrBits = { 613 if (HasHExtension) { 614 if (EnableSv48) 615 coreParams.GPAddrBitsSv48x4 616 else 617 coreParams.GPAddrBitsSv39x4 618 } else { 619 if (EnableSv48) 620 coreParams.VAddrBitsSv48 621 else 622 coreParams.VAddrBitsSv39 623 } 624 } // VAddrBits is Virtual Memory addr bits 625 626 def VAddrMaxBits = { 627 if(EnableSv48) { 628 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 629 } else { 630 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 631 } 632 } 633 634 def AsidLength = coreParams.AsidLength 635 def VmidLength = coreParams.VmidLength 636 def ReSelectLen = coreParams.ReSelectLen 637 def AddrBytes = AddrBits / 8 // unused 638 def DataBits = XLEN 639 def DataBytes = DataBits / 8 640 def QuadWordBits = DataBits * 2 641 def QuadWordBytes = QuadWordBits / 8 642 def VDataBytes = VLEN / 8 643 def HasFPU = coreParams.HasFPU 644 def HasVPU = coreParams.HasVPU 645 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 646 def FetchWidth = coreParams.FetchWidth 647 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 648 def EnableBPU = coreParams.EnableBPU 649 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 650 def EnableRAS = coreParams.EnableRAS 651 def EnableLB = coreParams.EnableLB 652 def EnableLoop = coreParams.EnableLoop 653 def EnableSC = coreParams.EnableSC 654 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 655 def HistoryLength = coreParams.HistoryLength 656 def EnableGHistDiff = coreParams.EnableGHistDiff 657 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 658 def EnableClockGate = coreParams.EnableClockGate 659 def UbtbGHRLength = coreParams.UbtbGHRLength 660 def UbtbSize = coreParams.UbtbSize 661 def EnableFauFTB = coreParams.EnableFauFTB 662 def FtbSize = coreParams.FtbSize 663 def FtbWays = coreParams.FtbWays 664 def FtbTagLength = coreParams.FtbTagLength 665 def RasSize = coreParams.RasSize 666 def RasSpecSize = coreParams.RasSpecSize 667 def RasCtrSize = coreParams.RasCtrSize 668 669 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 670 coreParams.branchPredictor(resp_in, p) 671 } 672 def numBr = coreParams.numBr 673 def TageTableInfos = coreParams.TageTableInfos 674 def TageBanks = coreParams.numBr 675 def SCNRows = coreParams.SCNRows 676 def SCCtrBits = coreParams.SCCtrBits 677 def SCHistLens = coreParams.SCHistLens 678 def SCNTables = coreParams.SCNTables 679 680 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 681 case ((n, cb), h) => (n, cb, h) 682 } 683 def ITTageTableInfos = coreParams.ITTageTableInfos 684 type FoldedHistoryInfo = Tuple2[Int, Int] 685 def foldedGHistInfos = 686 (TageTableInfos.map{ case (nRows, h, t) => 687 if (h > 0) 688 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 689 else 690 Set[FoldedHistoryInfo]() 691 }.reduce(_++_).toSet ++ 692 SCTableInfos.map{ case (nRows, _, h) => 693 if (h > 0) 694 Set((h, min(log2Ceil(nRows/TageBanks), h))) 695 else 696 Set[FoldedHistoryInfo]() 697 }.reduce(_++_).toSet ++ 698 ITTageTableInfos.map{ case (nRows, h, t) => 699 if (h > 0) 700 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 701 else 702 Set[FoldedHistoryInfo]() 703 }.reduce(_++_) ++ 704 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 705 ).toList 706 707 708 709 def CacheLineSize = coreParams.CacheLineSize 710 def CacheLineHalfWord = CacheLineSize / 16 711 def ExtHistoryLength = HistoryLength + 64 712 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 713 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 714 def IBufSize = coreParams.IBufSize 715 def IBufNBank = coreParams.IBufNBank 716 def backendParams: BackendParams = coreParams.backendParams 717 def DecodeWidth = coreParams.DecodeWidth 718 def RenameWidth = coreParams.RenameWidth 719 def CommitWidth = coreParams.CommitWidth 720 def RobCommitWidth = coreParams.RobCommitWidth 721 def RabCommitWidth = coreParams.RabCommitWidth 722 def MaxUopSize = coreParams.MaxUopSize 723 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 724 def RenameSnapshotNum = coreParams.RenameSnapshotNum 725 def FtqSize = coreParams.FtqSize 726 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 727 def IntLogicRegs = coreParams.IntLogicRegs 728 def FpLogicRegs = coreParams.FpLogicRegs 729 def VecLogicRegs = coreParams.VecLogicRegs 730 def V0LogicRegs = coreParams.V0LogicRegs 731 def VlLogicRegs = coreParams.VlLogicRegs 732 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 733 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 734 def V0_IDX = coreParams.V0_IDX 735 def Vl_IDX = coreParams.Vl_IDX 736 def IntPhyRegs = coreParams.intPreg.numEntries 737 def FpPhyRegs = coreParams.fpPreg.numEntries 738 def VfPhyRegs = coreParams.vfPreg.numEntries 739 def V0PhyRegs = coreParams.v0Preg.numEntries 740 def VlPhyRegs = coreParams.vlPreg.numEntries 741 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 742 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 743 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 744 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 745 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 746 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 747 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 748 def RobSize = coreParams.RobSize 749 def RabSize = coreParams.RabSize 750 def VTypeBufferSize = coreParams.VTypeBufferSize 751 def IntRegCacheSize = coreParams.IntRegCacheSize 752 def MemRegCacheSize = coreParams.MemRegCacheSize 753 def RegCacheSize = coreParams.RegCacheSize 754 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 755 /** 756 * the minimum element length of vector elements 757 */ 758 def minVecElen: Int = coreParams.minVecElen 759 760 /** 761 * the maximum number of elements in vector register 762 */ 763 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 764 765 def IntRefCounterWidth = log2Ceil(RobSize) 766 def LSQEnqWidth = RenameWidth 767 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 768 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 769 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 770 def LoadQueueRARSize = coreParams.LoadQueueRARSize 771 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 772 def RollbackGroupSize = coreParams.RollbackGroupSize 773 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 774 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 775 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 776 def StoreQueueSize = coreParams.StoreQueueSize 777 def StoreQueueForceWriteSbufferUpper = coreParams.StoreQueueSize - 4 778 def StoreQueueForceWriteSbufferLower = StoreQueueForceWriteSbufferUpper - 5 779 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 780 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 781 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 782 def VlsQueueSize = coreParams.VlsQueueSize 783 784 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 785 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 786 787 def NumRedirect = backendParams.numRedirect 788 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 789 def FtqRedirectAheadNum = NumRedirect 790 def IfuRedirectNum = coreParams.IfuRedirectNum 791 def LoadPipelineWidth = coreParams.LoadPipelineWidth 792 def StorePipelineWidth = coreParams.StorePipelineWidth 793 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 794 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 795 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 796 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 797 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 798 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 799 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 800 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 801 def StoreBufferSize = coreParams.StoreBufferSize 802 def StoreBufferThreshold = coreParams.StoreBufferThreshold 803 def EnsbufferWidth = coreParams.EnsbufferWidth 804 def LoadDependencyWidth = coreParams.LoadDependencyWidth 805 def VlMergeBufferSize = coreParams.VlMergeBufferSize 806 def VsMergeBufferSize = coreParams.VsMergeBufferSize 807 def UopWritebackWidth = coreParams.UopWritebackWidth 808 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 809 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 810 def VSegmentBufferSize = coreParams.VSegmentBufferSize 811 def VFOFBufferSize = coreParams.VFOFBufferSize 812 def UncacheBufferSize = coreParams.UncacheBufferSize 813 def UncacheBufferIndexWidth = log2Up(UncacheBufferSize) 814 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 815 def EnableFastForward = coreParams.EnableFastForward 816 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 817 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 818 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 819 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 820 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 821 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 822 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 823 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 824 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 825 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 826 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 827 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 828 def HasCMO = coreParams.HasCMO && p(EnableCHI) 829 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 830 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 831 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 832 def asidLen = coreParams.MMUAsidLen 833 def vmidLen = coreParams.MMUVmidLen 834 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 835 def refillBothTlb = coreParams.refillBothTlb 836 def iwpuParam = coreParams.iwpuParameters 837 def dwpuParam = coreParams.dwpuParameters 838 def itlbParams = coreParams.itlbParameters 839 def ldtlbParams = coreParams.ldtlbParameters 840 def sttlbParams = coreParams.sttlbParameters 841 def hytlbParams = coreParams.hytlbParameters 842 def pftlbParams = coreParams.pftlbParameters 843 def l2ToL1Params = coreParams.l2ToL1tlbParameters 844 def btlbParams = coreParams.btlbParameters 845 def l2tlbParams = coreParams.l2tlbParameters 846 def NumPerfCounters = coreParams.NumPerfCounters 847 848 def instBytes = if (HasCExtension) 2 else 4 849 def instOffsetBits = log2Ceil(instBytes) 850 851 def icacheParameters = coreParams.icacheParameters 852 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 853 854 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 855 // for constrained LR/SC loop 856 def LRSCCycles = 64 857 // for lr storm 858 def LRSCBackOff = 8 859 860 // cache hierarchy configurations 861 def l1BusDataWidth = 256 862 863 // load violation predict 864 def ResetTimeMax2Pow = 20 //1078576 865 def ResetTimeMin2Pow = 10 //1024 866 // wait table parameters 867 def WaitTableSize = 1024 868 def MemPredPCWidth = log2Up(WaitTableSize) 869 def LWTUse2BitCounter = true 870 // store set parameters 871 def SSITSize = WaitTableSize 872 def LFSTSize = 32 873 def SSIDWidth = log2Up(LFSTSize) 874 def LFSTWidth = 4 875 def StoreSetEnable = true // LWT will be disabled if SS is enabled 876 def LFSTEnable = true 877 878 def PCntIncrStep: Int = 6 879 def numPCntHc: Int = 12 880 def numPCntPtw: Int = 19 881 882 def numCSRPCntFrontend = 8 883 def numCSRPCntCtrl = 8 884 def numCSRPCntLsu = 8 885 def numCSRPCntHc = 5 886 def printEventCoding = true 887 def printCriticalError = false 888 def maxCommitStuck = pow(2, 21).toInt 889 890 // Vector load exception 891 def maxMergeNumPerCycle = 4 892 893 // Parameters for Sdtrig extension 894 protected def TriggerNum = 4 895 protected def TriggerChainMaxLength = 2 896 897 // Parameters for Trace extension 898 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 899 def CauseWidth = XLEN 900 def TvalWidth = coreParams.traceParams.IaddrWidth 901 def PrivWidth = coreParams.traceParams.PrivWidth 902 def IaddrWidth = coreParams.traceParams.IaddrWidth 903 def ItypeWidth = coreParams.traceParams.ItypeWidth 904 def IretireWidthInPipe = log2Up(RenameWidth * 2) 905 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 906 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 907} 908