1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBitsSv39: Int = 39, 72 GPAddrBitsSv39x4: Int = 41, 73 VAddrBitsSv48: Int = 48, 74 GPAddrBitsSv48x4: Int = 50, 75 HasFPU: Boolean = true, 76 HasVPU: Boolean = true, 77 HasCustomCSRCacheOp: Boolean = true, 78 FetchWidth: Int = 8, 79 AsidLength: Int = 16, 80 VmidLength: Int = 14, 81 EnableBPU: Boolean = true, 82 EnableBPD: Boolean = true, 83 EnableRAS: Boolean = true, 84 EnableLB: Boolean = false, 85 EnableLoop: Boolean = true, 86 EnableSC: Boolean = true, 87 EnbaleTlbDebug: Boolean = false, 88 EnableClockGate: Boolean = true, 89 EnableJal: Boolean = false, 90 EnableFauFTB: Boolean = true, 91 EnableSv48: Boolean = true, 92 UbtbGHRLength: Int = 4, 93 // HistoryLength: Int = 512, 94 EnableGHistDiff: Boolean = true, 95 EnableCommitGHistDiff: Boolean = true, 96 UbtbSize: Int = 256, 97 FtbSize: Int = 2048, 98 RasSize: Int = 16, 99 RasSpecSize: Int = 32, 100 RasCtrSize: Int = 3, 101 CacheLineSize: Int = 512, 102 FtbWays: Int = 4, 103 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 104 // Sets Hist Tag 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 122 (resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val uftb = Module(new FauFTB()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(uftb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 132 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 133 134 uftb.io.in.bits.resp_in(0) := resp_in 135 tage.io.in.bits.resp_in(0) := uftb.io.out 136 ftb.io.in.bits.resp_in(0) := tage.io.out 137 ittage.io.in.bits.resp_in(0) := ftb.io.out 138 ras.io.in.bits.resp_in(0) := ittage.io.out 139 140 (preds, ras.io.out) 141 }, 142 ICacheForceMetaECCError: Boolean = false, 143 ICacheForceDataECCError: Boolean = false, 144 IBufSize: Int = 48, 145 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 146 DecodeWidth: Int = 6, 147 RenameWidth: Int = 6, 148 CommitWidth: Int = 8, 149 RobCommitWidth: Int = 8, 150 RabCommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 15, // 15: tmp 159 V0LogicRegs: Int = 1, // V0 160 VlLogicRegs: Int = 1, // Vl 161 V0_IDX: Int = 0, 162 Vl_IDX: Int = 0, 163 NRPhyRegs: Int = 192, 164 VirtualLoadQueueSize: Int = 72, 165 LoadQueueRARSize: Int = 72, 166 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 167 RollbackGroupSize: Int = 8, 168 LoadQueueReplaySize: Int = 72, 169 LoadUncacheBufferSize: Int = 20, 170 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 171 StoreQueueSize: Int = 64, 172 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 173 StoreQueueForwardWithMask: Boolean = true, 174 VlsQueueSize: Int = 8, 175 RobSize: Int = 160, 176 RabSize: Int = 256, 177 VTypeBufferSize: Int = 64, // used to reorder vtype 178 IssueQueueSize: Int = 24, 179 IssueQueueCompEntrySize: Int = 16, 180 dpParams: DispatchParameters = DispatchParameters( 181 IntDqSize = 16, 182 FpDqSize = 16, 183 LsDqSize = 18, 184 IntDqDeqWidth = 8, 185 FpDqDeqWidth = 6, 186 VecDqDeqWidth = 6, 187 LsDqDeqWidth = 6, 188 ), 189 intPreg: PregParams = IntPregParams( 190 numEntries = 224, 191 numRead = None, 192 numWrite = None, 193 ), 194 fpPreg: PregParams = FpPregParams( 195 numEntries = 192, 196 numRead = None, 197 numWrite = None, 198 ), 199 vfPreg: VfPregParams = VfPregParams( 200 numEntries = 128, 201 numRead = None, 202 numWrite = None, 203 ), 204 v0Preg: V0PregParams = V0PregParams( 205 numEntries = 22, 206 numRead = None, 207 numWrite = None, 208 ), 209 vlPreg: VlPregParams = VlPregParams( 210 numEntries = 32, 211 numRead = None, 212 numWrite = None, 213 ), 214 IntRegCacheSize: Int = 16, 215 MemRegCacheSize: Int = 12, 216 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 217 IfuRedirectNum: Int = 1, 218 LoadPipelineWidth: Int = 3, 219 StorePipelineWidth: Int = 2, 220 VecLoadPipelineWidth: Int = 2, 221 VecStorePipelineWidth: Int = 2, 222 VecMemSrcInWidth: Int = 2, 223 VecMemInstWbWidth: Int = 1, 224 VecMemDispatchWidth: Int = 1, 225 VecMemDispatchMaxNumber: Int = 16, 226 VecMemUnitStrideMaxFlowNum: Int = 2, 227 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 228 StoreBufferSize: Int = 16, 229 StoreBufferThreshold: Int = 7, 230 EnsbufferWidth: Int = 2, 231 LoadDependencyWidth: Int = 2, 232 // ============ VLSU ============ 233 VlMergeBufferSize: Int = 16, 234 VsMergeBufferSize: Int = 16, 235 UopWritebackWidth: Int = 2, 236 VLUopWritebackWidth: Int = 2, 237 VSUopWritebackWidth: Int = 1, 238 VSegmentBufferSize: Int = 8, 239 VFOFBufferSize: Int = 8, 240 VLFOFWritebackWidth: Int = 1, 241 // ============================== 242 UncacheBufferSize: Int = 4, 243 EnableLoadToLoadForward: Boolean = false, 244 EnableFastForward: Boolean = true, 245 EnableLdVioCheckAfterReset: Boolean = true, 246 EnableSoftPrefetchAfterReset: Boolean = true, 247 EnableCacheErrorAfterReset: Boolean = true, 248 EnableAccurateLoadError: Boolean = false, 249 EnableUncacheWriteOutstanding: Boolean = false, 250 EnableHardwareStoreMisalign: Boolean = true, 251 EnableHardwareLoadMisalign: Boolean = true, 252 EnableStorePrefetchAtIssue: Boolean = false, 253 EnableStorePrefetchAtCommit: Boolean = false, 254 EnableAtCommitMissTrigger: Boolean = true, 255 EnableStorePrefetchSMS: Boolean = false, 256 EnableStorePrefetchSPB: Boolean = false, 257 HasCMO: Boolean = true, 258 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 259 MMUVmidLen: Int = 14, 260 ReSelectLen: Int = 7, // load replay queue replay select counter len 261 iwpuParameters: WPUParameters = WPUParameters( 262 enWPU = false, 263 algoName = "mmru", 264 isICache = true, 265 ), 266 dwpuParameters: WPUParameters = WPUParameters( 267 enWPU = false, 268 algoName = "mmru", 269 enCfPred = false, 270 isICache = false, 271 ), 272 itlbParameters: TLBParameters = TLBParameters( 273 name = "itlb", 274 fetchi = true, 275 useDmode = false, 276 NWays = 48, 277 ), 278 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 279 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 280 ldtlbParameters: TLBParameters = TLBParameters( 281 name = "ldtlb", 282 NWays = 48, 283 outReplace = false, 284 partialStaticPMP = true, 285 outsideRecvFlush = true, 286 saveLevel = false, 287 lgMaxSize = 4 288 ), 289 sttlbParameters: TLBParameters = TLBParameters( 290 name = "sttlb", 291 NWays = 48, 292 outReplace = false, 293 partialStaticPMP = true, 294 outsideRecvFlush = true, 295 saveLevel = false, 296 lgMaxSize = 4 297 ), 298 hytlbParameters: TLBParameters = TLBParameters( 299 name = "hytlb", 300 NWays = 48, 301 outReplace = false, 302 partialStaticPMP = true, 303 outsideRecvFlush = true, 304 saveLevel = false, 305 lgMaxSize = 4 306 ), 307 pftlbParameters: TLBParameters = TLBParameters( 308 name = "pftlb", 309 NWays = 48, 310 outReplace = false, 311 partialStaticPMP = true, 312 outsideRecvFlush = true, 313 saveLevel = false, 314 lgMaxSize = 4 315 ), 316 l2ToL1tlbParameters: TLBParameters = TLBParameters( 317 name = "l2tlb", 318 NWays = 48, 319 outReplace = false, 320 partialStaticPMP = true, 321 outsideRecvFlush = true, 322 saveLevel = false 323 ), 324 refillBothTlb: Boolean = false, 325 btlbParameters: TLBParameters = TLBParameters( 326 name = "btlb", 327 NWays = 48, 328 ), 329 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 330 NumPerfCounters: Int = 16, 331 icacheParameters: ICacheParameters = ICacheParameters( 332 tagECC = Some("parity"), 333 dataECC = Some("parity"), 334 replacer = Some("setplru"), 335 ), 336 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 337 tagECC = Some("secded"), 338 dataECC = Some("secded"), 339 replacer = Some("setplru"), 340 nMissEntries = 16, 341 nProbeEntries = 8, 342 nReleaseEntries = 18, 343 nMaxPrefetchEntry = 6, 344 )), 345 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 346 name = "l2", 347 ways = 8, 348 sets = 1024, // default 512KB L2 349 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 350 coupledL2.prefetch.TPParameters()), 351 )), 352 L2NBanks: Int = 1, 353 usePTWRepeater: Boolean = false, 354 softTLB: Boolean = false, // dpi-c l1tlb debug only 355 softPTW: Boolean = false, // dpi-c l2tlb debug only 356 softPTWDelay: Int = 1 357){ 358 def vlWidth = log2Up(VLEN) + 1 359 360 /** 361 * the minimum element length of vector elements 362 */ 363 val minVecElen: Int = 8 364 365 /** 366 * the maximum number of elements in vector register 367 */ 368 val maxElemPerVreg: Int = VLEN / minVecElen 369 370 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 371 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 372 373 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 374 val RegCacheIdxWidth = log2Up(RegCacheSize) 375 376 val intSchdParams = { 377 implicit val schdType: SchedulerType = IntScheduler() 378 SchdBlockParams(Seq( 379 IssueBlockParams(Seq( 380 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 381 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 382 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 383 IssueBlockParams(Seq( 384 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 385 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 386 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 387 IssueBlockParams(Seq( 388 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 389 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 390 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 391 IssueBlockParams(Seq( 392 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 393 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 394 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 395 ), 396 numPregs = intPreg.numEntries, 397 numDeqOutside = 0, 398 schdType = schdType, 399 rfDataWidth = intPreg.dataCfg.dataWidth, 400 numUopIn = dpParams.IntDqDeqWidth, 401 ) 402 } 403 404 val fpSchdParams = { 405 implicit val schdType: SchedulerType = FpScheduler() 406 SchdBlockParams(Seq( 407 IssueBlockParams(Seq( 408 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 409 ), numEntries = 18, numEnq = 2, numComp = 16), 410 IssueBlockParams(Seq( 411 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 412 ), numEntries = 18, numEnq = 2, numComp = 16), 413 IssueBlockParams(Seq( 414 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 415 ), numEntries = 18, numEnq = 2, numComp = 16), 416 IssueBlockParams(Seq( 417 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 418 ), numEntries = 18, numEnq = 2, numComp = 16), 419 IssueBlockParams(Seq( 420 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 421 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 422 ), numEntries = 18, numEnq = 2, numComp = 16), 423 ), 424 numPregs = fpPreg.numEntries, 425 numDeqOutside = 0, 426 schdType = schdType, 427 rfDataWidth = fpPreg.dataCfg.dataWidth, 428 numUopIn = dpParams.FpDqDeqWidth, 429 ) 430 } 431 432 val vfSchdParams = { 433 implicit val schdType: SchedulerType = VfScheduler() 434 SchdBlockParams(Seq( 435 IssueBlockParams(Seq( 436 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 437 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 438 ), numEntries = 16, numEnq = 2, numComp = 14), 439 IssueBlockParams(Seq( 440 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 441 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 442 ), numEntries = 16, numEnq = 2, numComp = 14), 443 IssueBlockParams(Seq( 444 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 445 ), numEntries = 10, numEnq = 2, numComp = 8), 446 ), 447 numPregs = vfPreg.numEntries, 448 numDeqOutside = 0, 449 schdType = schdType, 450 rfDataWidth = vfPreg.dataCfg.dataWidth, 451 numUopIn = dpParams.VecDqDeqWidth, 452 ) 453 } 454 455 val memSchdParams = { 456 implicit val schdType: SchedulerType = MemScheduler() 457 val rfDataWidth = 64 458 459 SchdBlockParams(Seq( 460 IssueBlockParams(Seq( 461 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 462 ), numEntries = 16, numEnq = 1, numComp = 15), 463 IssueBlockParams(Seq( 464 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 465 ), numEntries = 16, numEnq = 1, numComp = 15), 466 IssueBlockParams(Seq( 467 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 468 ), numEntries = 16, numEnq = 1, numComp = 15), 469 IssueBlockParams(Seq( 470 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 471 ), numEntries = 16, numEnq = 1, numComp = 15), 472 IssueBlockParams(Seq( 473 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 474 ), numEntries = 16, numEnq = 1, numComp = 15), 475 IssueBlockParams(Seq( 476 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 477 ), numEntries = 16, numEnq = 1, numComp = 15), 478 IssueBlockParams(Seq( 479 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 480 ), numEntries = 16, numEnq = 1, numComp = 15), 481 IssueBlockParams(Seq( 482 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 483 ), numEntries = 16, numEnq = 1, numComp = 15), 484 IssueBlockParams(Seq( 485 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 486 ), numEntries = 16, numEnq = 1, numComp = 15), 487 ), 488 numPregs = intPreg.numEntries max vfPreg.numEntries, 489 numDeqOutside = 0, 490 schdType = schdType, 491 rfDataWidth = rfDataWidth, 492 numUopIn = dpParams.LsDqDeqWidth, 493 ) 494 } 495 496 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 497 498 def iqWakeUpParams = { 499 Seq( 500 WakeUpConfig( 501 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 502 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 503 ), 504 // TODO: add load -> fp slow wakeup 505 WakeUpConfig( 506 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 507 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 508 ), 509 WakeUpConfig( 510 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 511 Seq("STD0", "STD1") 512 ), 513// WakeUpConfig( 514// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 515// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 516// ), 517 ).flatten 518 } 519 520 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 521 522 val backendParams: BackendParams = backend.BackendParams( 523 Map( 524 IntScheduler() -> intSchdParams, 525 FpScheduler() -> fpSchdParams, 526 VfScheduler() -> vfSchdParams, 527 MemScheduler() -> memSchdParams, 528 ), 529 Seq( 530 intPreg, 531 fpPreg, 532 vfPreg, 533 v0Preg, 534 vlPreg, 535 fakeIntPreg 536 ), 537 iqWakeUpParams, 538 ) 539 540 // Parameters for trace extension. 541 // Trace parameters is useful for XSTOP. 542 val TraceGroupNum = 3 // Width to Encoder 543} 544 545case object DebugOptionsKey extends Field[DebugOptions] 546 547case class DebugOptions 548( 549 FPGAPlatform: Boolean = false, 550 ResetGen: Boolean = false, 551 EnableDifftest: Boolean = false, 552 AlwaysBasicDiff: Boolean = true, 553 EnableDebug: Boolean = false, 554 EnablePerfDebug: Boolean = true, 555 UseDRAMSim: Boolean = false, 556 EnableConstantin: Boolean = false, 557 EnableChiselDB: Boolean = false, 558 AlwaysBasicDB: Boolean = true, 559 EnableRollingDB: Boolean = false 560) 561 562trait HasXSParameter { 563 564 implicit val p: Parameters 565 566 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 567 def PmemRanges = p(SoCParamsKey).PmemRanges 568 def PmemLowBounds = PmemRanges.unzip._1 569 def PmemHighBounds = PmemRanges.unzip._2 570 final val PageOffsetWidth = 12 571 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 572 573 def coreParams = p(XSCoreParamsKey) 574 def env = p(DebugOptionsKey) 575 576 def XLEN = coreParams.XLEN 577 def VLEN = coreParams.VLEN 578 def ELEN = coreParams.ELEN 579 def HSXLEN = coreParams.HSXLEN 580 val minFLen = 32 581 val fLen = 64 582 def hartIdLen = p(MaxHartIdBits) 583 val xLen = XLEN 584 585 def HasMExtension = coreParams.HasMExtension 586 def HasCExtension = coreParams.HasCExtension 587 def HasHExtension = coreParams.HasHExtension 588 def EnableSv48 = coreParams.EnableSv48 589 def HasDiv = coreParams.HasDiv 590 def HasIcache = coreParams.HasICache 591 def HasDcache = coreParams.HasDCache 592 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 593 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 594 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 595 def GPAddrBits = { 596 if (EnableSv48) 597 coreParams.GPAddrBitsSv48x4 598 else 599 coreParams.GPAddrBitsSv39x4 600 } 601 def VAddrBits = { 602 if (HasHExtension) { 603 if (EnableSv48) 604 coreParams.GPAddrBitsSv48x4 605 else 606 coreParams.GPAddrBitsSv39x4 607 } else { 608 if (EnableSv48) 609 coreParams.VAddrBitsSv48 610 else 611 coreParams.VAddrBitsSv39 612 } 613 } // VAddrBits is Virtual Memory addr bits 614 615 def VAddrMaxBits = { 616 if(EnableSv48) { 617 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 618 } else { 619 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 620 } 621 } 622 623 def AsidLength = coreParams.AsidLength 624 def VmidLength = coreParams.VmidLength 625 def ReSelectLen = coreParams.ReSelectLen 626 def AddrBytes = AddrBits / 8 // unused 627 def DataBits = XLEN 628 def DataBytes = DataBits / 8 629 def VDataBytes = VLEN / 8 630 def HasFPU = coreParams.HasFPU 631 def HasVPU = coreParams.HasVPU 632 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 633 def FetchWidth = coreParams.FetchWidth 634 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 635 def EnableBPU = coreParams.EnableBPU 636 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 637 def EnableRAS = coreParams.EnableRAS 638 def EnableLB = coreParams.EnableLB 639 def EnableLoop = coreParams.EnableLoop 640 def EnableSC = coreParams.EnableSC 641 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 642 def HistoryLength = coreParams.HistoryLength 643 def EnableGHistDiff = coreParams.EnableGHistDiff 644 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 645 def EnableClockGate = coreParams.EnableClockGate 646 def UbtbGHRLength = coreParams.UbtbGHRLength 647 def UbtbSize = coreParams.UbtbSize 648 def EnableFauFTB = coreParams.EnableFauFTB 649 def FtbSize = coreParams.FtbSize 650 def FtbWays = coreParams.FtbWays 651 def RasSize = coreParams.RasSize 652 def RasSpecSize = coreParams.RasSpecSize 653 def RasCtrSize = coreParams.RasCtrSize 654 655 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 656 coreParams.branchPredictor(resp_in, p) 657 } 658 def numBr = coreParams.numBr 659 def TageTableInfos = coreParams.TageTableInfos 660 def TageBanks = coreParams.numBr 661 def SCNRows = coreParams.SCNRows 662 def SCCtrBits = coreParams.SCCtrBits 663 def SCHistLens = coreParams.SCHistLens 664 def SCNTables = coreParams.SCNTables 665 666 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 667 case ((n, cb), h) => (n, cb, h) 668 } 669 def ITTageTableInfos = coreParams.ITTageTableInfos 670 type FoldedHistoryInfo = Tuple2[Int, Int] 671 def foldedGHistInfos = 672 (TageTableInfos.map{ case (nRows, h, t) => 673 if (h > 0) 674 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 675 else 676 Set[FoldedHistoryInfo]() 677 }.reduce(_++_).toSet ++ 678 SCTableInfos.map{ case (nRows, _, h) => 679 if (h > 0) 680 Set((h, min(log2Ceil(nRows/TageBanks), h))) 681 else 682 Set[FoldedHistoryInfo]() 683 }.reduce(_++_).toSet ++ 684 ITTageTableInfos.map{ case (nRows, h, t) => 685 if (h > 0) 686 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 687 else 688 Set[FoldedHistoryInfo]() 689 }.reduce(_++_) ++ 690 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 691 ).toList 692 693 694 695 def CacheLineSize = coreParams.CacheLineSize 696 def CacheLineHalfWord = CacheLineSize / 16 697 def ExtHistoryLength = HistoryLength + 64 698 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 699 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 700 def IBufSize = coreParams.IBufSize 701 def IBufNBank = coreParams.IBufNBank 702 def backendParams: BackendParams = coreParams.backendParams 703 def DecodeWidth = coreParams.DecodeWidth 704 def RenameWidth = coreParams.RenameWidth 705 def CommitWidth = coreParams.CommitWidth 706 def RobCommitWidth = coreParams.RobCommitWidth 707 def RabCommitWidth = coreParams.RabCommitWidth 708 def MaxUopSize = coreParams.MaxUopSize 709 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 710 def RenameSnapshotNum = coreParams.RenameSnapshotNum 711 def FtqSize = coreParams.FtqSize 712 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 713 def IntLogicRegs = coreParams.IntLogicRegs 714 def FpLogicRegs = coreParams.FpLogicRegs 715 def VecLogicRegs = coreParams.VecLogicRegs 716 def V0LogicRegs = coreParams.V0LogicRegs 717 def VlLogicRegs = coreParams.VlLogicRegs 718 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 719 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 720 def V0_IDX = coreParams.V0_IDX 721 def Vl_IDX = coreParams.Vl_IDX 722 def IntPhyRegs = coreParams.intPreg.numEntries 723 def FpPhyRegs = coreParams.fpPreg.numEntries 724 def VfPhyRegs = coreParams.vfPreg.numEntries 725 def V0PhyRegs = coreParams.v0Preg.numEntries 726 def VlPhyRegs = coreParams.vlPreg.numEntries 727 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 728 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 729 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 730 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 731 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 732 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 733 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 734 def RobSize = coreParams.RobSize 735 def RabSize = coreParams.RabSize 736 def VTypeBufferSize = coreParams.VTypeBufferSize 737 def IntRegCacheSize = coreParams.IntRegCacheSize 738 def MemRegCacheSize = coreParams.MemRegCacheSize 739 def RegCacheSize = coreParams.RegCacheSize 740 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 741 /** 742 * the minimum element length of vector elements 743 */ 744 def minVecElen: Int = coreParams.minVecElen 745 746 /** 747 * the maximum number of elements in vector register 748 */ 749 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 750 751 def IntRefCounterWidth = log2Ceil(RobSize) 752 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 753 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 754 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 755 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 756 def LoadQueueRARSize = coreParams.LoadQueueRARSize 757 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 758 def RollbackGroupSize = coreParams.RollbackGroupSize 759 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 760 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 761 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 762 def StoreQueueSize = coreParams.StoreQueueSize 763 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 764 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 765 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 766 def VlsQueueSize = coreParams.VlsQueueSize 767 def dpParams = coreParams.dpParams 768 769 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 770 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 771 772 def NumRedirect = backendParams.numRedirect 773 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 774 def FtqRedirectAheadNum = NumRedirect 775 def IfuRedirectNum = coreParams.IfuRedirectNum 776 def LoadPipelineWidth = coreParams.LoadPipelineWidth 777 def StorePipelineWidth = coreParams.StorePipelineWidth 778 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 779 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 780 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 781 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 782 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 783 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 784 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 785 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 786 def StoreBufferSize = coreParams.StoreBufferSize 787 def StoreBufferThreshold = coreParams.StoreBufferThreshold 788 def EnsbufferWidth = coreParams.EnsbufferWidth 789 def LoadDependencyWidth = coreParams.LoadDependencyWidth 790 def VlMergeBufferSize = coreParams.VlMergeBufferSize 791 def VsMergeBufferSize = coreParams.VsMergeBufferSize 792 def UopWritebackWidth = coreParams.UopWritebackWidth 793 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 794 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 795 def VSegmentBufferSize = coreParams.VSegmentBufferSize 796 def VFOFBufferSize = coreParams.VFOFBufferSize 797 def UncacheBufferSize = coreParams.UncacheBufferSize 798 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 799 def EnableFastForward = coreParams.EnableFastForward 800 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 801 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 802 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 803 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 804 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 805 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 806 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 807 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 808 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 809 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 810 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 811 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 812 def HasCMO = coreParams.HasCMO && p(EnableCHI) 813 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 814 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 815 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 816 def asidLen = coreParams.MMUAsidLen 817 def vmidLen = coreParams.MMUVmidLen 818 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 819 def refillBothTlb = coreParams.refillBothTlb 820 def iwpuParam = coreParams.iwpuParameters 821 def dwpuParam = coreParams.dwpuParameters 822 def itlbParams = coreParams.itlbParameters 823 def ldtlbParams = coreParams.ldtlbParameters 824 def sttlbParams = coreParams.sttlbParameters 825 def hytlbParams = coreParams.hytlbParameters 826 def pftlbParams = coreParams.pftlbParameters 827 def l2ToL1Params = coreParams.l2ToL1tlbParameters 828 def btlbParams = coreParams.btlbParameters 829 def l2tlbParams = coreParams.l2tlbParameters 830 def NumPerfCounters = coreParams.NumPerfCounters 831 832 def instBytes = if (HasCExtension) 2 else 4 833 def instOffsetBits = log2Ceil(instBytes) 834 835 def icacheParameters = coreParams.icacheParameters 836 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 837 838 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 839 // for constrained LR/SC loop 840 def LRSCCycles = 64 841 // for lr storm 842 def LRSCBackOff = 8 843 844 // cache hierarchy configurations 845 def l1BusDataWidth = 256 846 847 // load violation predict 848 def ResetTimeMax2Pow = 20 //1078576 849 def ResetTimeMin2Pow = 10 //1024 850 // wait table parameters 851 def WaitTableSize = 1024 852 def MemPredPCWidth = log2Up(WaitTableSize) 853 def LWTUse2BitCounter = true 854 // store set parameters 855 def SSITSize = WaitTableSize 856 def LFSTSize = 32 857 def SSIDWidth = log2Up(LFSTSize) 858 def LFSTWidth = 4 859 def StoreSetEnable = true // LWT will be disabled if SS is enabled 860 def LFSTEnable = true 861 862 def PCntIncrStep: Int = 6 863 def numPCntHc: Int = 12 864 def numPCntPtw: Int = 19 865 866 def numCSRPCntFrontend = 8 867 def numCSRPCntCtrl = 8 868 def numCSRPCntLsu = 8 869 def numCSRPCntHc = 5 870 def printEventCoding = true 871 872 // Vector load exception 873 def maxMergeNumPerCycle = 4 874 875 // Parameters for Sdtrig extension 876 protected def TriggerNum = 4 877 protected def TriggerChainMaxLength = 2 878 879 // Parameters for Trace extension 880 def TraceGroupNum = coreParams.TraceGroupNum 881} 882